IEEE Solid-States Circuits Magazine - Fall 2020 - 52

step begins only once the previous one
is complete. The benefit of this method
is that all features and specifications
from prior steps are complete and static
between design stages, preventing
last-minute miscommunications and

specification changes. The downside
is that each chip design step can take
months from specification to comple-
tion. These timescales work well for
applications where compute demands
grow at a rate similar to Moore's law,

Design
Specification
Architectural
Modeling

RTL Design

Verification
and Validation

Physical Design

Firmware/Software
Time

FIGURE 4: The waterfall hardware design model, where each previous step is completed
before starting the next one. RTL: register-transfer level.

Sprint 0
Design
Specification
Architectural
Modeling
RTL Design
Verification
and Validation
Physical
Design
Firmware/
Software

Sprint 1

Sprint N

...

F0
F0

...

Time
FIGURE 5: The agile hardware design flow, where features (F) of each design step are
completed iteratively during each project sprint such that a functional GDS is always ready
for tapeout.

FA L L 2 0 2 0

IEEE SOLID-STATE CIRCUITS MAGAZINE

but the requirements of e
- merging
applications often outpace ASIC de-
-
sign schedules. Looking more specif-
ically at machine learning, between
2012 and 2018, the compute demand
grew by roughly 300,000 × [8]. This
would indicate that the compute
demand in machine learning doubles
every 3.5 months, much faster than tra-
ditionally allowed for by Moore's law.
In this type of scenario with short-
ened product lifecycles, we need
rapid new spins of silicon to keep
pace with innovations in architec-
tures and algorithms.
Another observation (in this case,
from the EDA community) that moti-
vates the move to more agile prac-
tices is the concept of " shifting left, "
which states that tasks once per-
formed sequentially must now be
done in parallel due to a tightening of
dependencies [9]. Multiple markets,
such as machine learning, are seeing
design timescales squeezed and the
time to market decrease, leading to
the introduction of similar design
philosophies. Due to this, new meth-
odologies and processes are needed
to address emerging application de---
mands on short timescales while
still minimizing the chance of costly
errors and bugs. Agile -development
was proposed in the software com-
munity in 2001 and specifies an itera-
tive refinement of a set of working
design prototypes as opposed to com-
pleting each step in the design pro-
cess sequentially and in full. A benefit
of agile design is that there is always
a viable development point after a
single " sprint " or a repeatable fixed
time window during which a " done "
version of the architecture is created,
as illustrated in Figure 5.
In our inference accelerator agile
hardware methodology, we started
the design process using a trivial pro-
totype with a minimal working feature
set, employing this design to pipeclean the toolflows and scripts used
later in the design process and reduc-
ing the chance of last-minute and
unforeseen tool and scripting errors.
Additionally, energy consumption
and performance were monitored

IEEE Solid-States Circuits Magazine - Fall 2020

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