IEEE Solid-States Circuits Magazine - Fall 2020 - 53

in an iterative fashion, facilitating early
and frequent feedback to the register-
transfer-level (RTL) design engineers
about microarchitecture tweaks to
improve the quality of the results. After
this initial prototype was completed,
features were iteratively added, ap-
-
proaching the project deadline with
a tapeout ready candidate available
at each stage of the process. As a
result, there was a lower chance of
grossly underestimating the time
required for the design, improving
our ability to effectively schedule
the project.
When moving a team to an agile
hardware design flow, many existing
software tools are available for project
management and task planning. One
of the most widely used is Atlassian's
Jira, a cross-platform agile software
development and team collaboration
tool. It helps agile teams plan and
track issues and projects so that they
can deliver on time. There are also
many free and open source alterna-
tives for agile project management,
with Github incorporating many of the
same capabilities into its platforms at
no cost. Always having a viable design
ready for tapeout necessitates auto-
mation of the toolflows triggered by
code check-ins and scheduled nightly
runs. These types of push-button
flows for running simulations, synthe-
sis, and place-and-route can be devel-
oped using continuous integration,
delivery, and deployment tools, such
as Jenkins and Bamboo, and reduce
design time overheads, significantly
improving productivity.

Higher-Abstraction
-Hardware -Design
Software systems rely on reuse that
is enabled by free and widely avail-
able libraries written in frequently
used and well-documented program-
ming languages. In contrast, most
hardware design flows depend on
infrequently employed p
- rimitive
languages to describe hardware, with
a process including many propri-
etary tools and process design kits
(PDKs), making design sharing and
reuse difficult. HDLs, such as Ver-

	

ilog, are used to describe cycleaccurate hardware, leading to a focus
on creating a single high-quality
instance of a design versus a flex-
ible, parameterizable component
that can be reused. In addition, cur-
rent long tool runtimes and develop-
ment cycles exacerbate the problem
of design space exploration by further
increasing the time from the design
capture to analyzing results.
Increasingly, common high-level
languages are being used as HDLs to
improve design productivity by clos-
ing the gap between software devel-
opment and circuit design. High-level
language approaches are often split
into two categories: HLS and hardware
generation [11]. HLS involves writing
untimed or loosely timed programs
in a high-level language, such as C++,
which are automatically synthesized
to a cycle-accurate specification in
an HDL, such as Verilog or VHDL,
given a set of design constraints. This
contrasts with hardware generation
approaches, where a hardware-ori-
ented description is written in a highlevel language and this description is
translated directly into an HDL. An
example of the latter is the Chisel lan-
guage developed at the University of
California, Berkeley.
The inference accelerator pre-
sented here employed an HLS flow
to model and design all on-chip digi-
tal logic. A commercial HLS tool used
loosely timed and untimed C/C++
architectural models to generate a syn-
thesizable Verilog RTL for application in
standard VLSI flows. Given a functional
description, finding a suitable microar-
chitecture is not a simple task, and dis-
covering an optimal one with respect to
designer constraints is even more chal-
lenging. HLS takes what was previously
a manual task and automates the pro-
cess of microarchitectural searching. It
can derive from a single piece of source
code a variety of microarchitectures
with different area and performance
characteristics, enabling rapid design
space exploration.
Figure 6 presents a typical HLS
flow for generating and verifying
the RTL used in the design of the

inference accelerator. Designs, test
benches, and reusable libraries
are implemented in a high-level C++
model and verified for functionality
and performance in C++ simulation.
Port and channel primitives from
the MatchLib library were used to
implement LI interfaces for all parti-
tions. LI interfacing reduces design
and verification effort by introduc-
ing a correct-by-construction design
strategy, wherein individual modules
are patient and capable of tolerating
arbitrary latencies at their inputs and
outputs while still producing a func-
tionally correct result [12]. LI design
also enables the decoupling of compu-
tation and communication to provide
flexibility in the physical implemen-
tation and reduce the timing closure
effort, as internal changes to an LIinterfaced module do not impact sys-
tem-level timing. This LI design model
complements HLS where the latencies
of individual units are determined
by design constraints and not fixed
within the high-level source.
Beyond developing methodologies
that improve circuit design modularity
and reuse, there are additional bene-
fits to increasing the level of abstrac-
tion of the hardware model. Moving
hardware description to a higher level
provided an opportunity for faster
simulation using free C++ compilation
and " simulation " using the GCC tool-
chain. Simulation speedup gains for
designs used in the inference accel-
erator are given in Figure 7. Across a
regression, 3-14× speedups are
achieved compared to a state-of-theart commercial HDL simulator. These
speedups, combined with the lack
of tool license overheads, provide an
opportunity for more run paralleliza-
tion and faster regressions, reducing
the feedback loop time for verification.
Even if a higher-level language is not
directly used for the design, there are
examples of HDLs being converted to
higher-level languages solely for the
simulation speedup benefits they offer,
such as Tesla's design flow, which uses
Verilator to convert the RTL to C++ for
up to a 30× speedup compared to a
commercial RTL simulator [13].

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IEEE Solid-States Circuits Magazine - Fall 2020

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