IEEE Solid-States Circuits Magazine - Fall 2020 - 56
3D NAND Memory
and Its Application
in Solid-State
Drives
Yan Li
Architecture,
reliability,
flash management
techniques, and
current trends
I
n the past 20 years,
NAND flash has under-
gone dramatic scaling,
with 2D NAND feature
size going from 400 nm
in 1998 to 15 nm in 2012 and 3D NAND
increasing from 24 layers to 128 layers
in just the past seven years. NAND
density, expressed in terms of gigabits
per square millimeter, has increased
100,000 times in the past 22 years [1].
Digital Object Identifier 10.1109/MSSC.2020.3021841
Date of current version: 18 November 2020
56
FA L L 2 0 2 0
Aside from physical scaling, NAND
logical scaling has also undergone a
transformation, evolving from sin-
gle-level cell (SLC) to two bits per cell
(MLC) to triple-level cell (TLC) and now
four bits per cell (QLC), which has
been incorporated into many prod-
ucts. NAND die capacity has grown
from 128 Mb in 2000 to 1.33 Tb in
2020. With the dramatic scaling of
NAND memory, the cost per gigabyte
of memory has been dramatically
reduced. The first wide adaptation
of NAND flash started in 2005, when
IEEE SOLID-STATE CIRCUITS MAGAZINE
Apple's iPod used NAND
flash instead of a micro
hard disk drive (HDD). The
two major advantages o f
NAND flash for mobile
applications are compact-
ness and no moving parts.
It is now easy to place
1 TB of NAND memory into
a small package, such as
a micro SD card. A solid-
state drive (SSD) can pack
64 TB or more into a stan-
dard nonvolatile memory
express (NVMe) drive with
hundreds of NAND chips. In
this digital age of zettabyte
data, big data applications
need larger storage capac-
ity and faster speeds to
access the data.
NAND's capability for
continued scaling comes
from its unique structure of chaining
the memory cells into long chains,
and these chains are now in mass
production, with up to 128 cells in
one string. It is predicted that the
length will increase to >500 cells in
one string, thus producing larger-
capacity storage chips with small
dimensions (<100 mm2). This article
is intended as a tutorial to intro-
duce NAND fundamentals related to
architecture, reliability, and flash
management techniques in SSD appli-
cations and to discuss current trends
1943-0582/20©2020IEEE
IEEE Solid-States Circuits Magazine - Fall 2020
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2020
Contents
IEEE Solid-States Circuits Magazine - Fall 2020 - Cover1
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IEEE Solid-States Circuits Magazine - Fall 2020 - Contents
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