IEEE Solid-States Circuits Magazine - Fall 2020 - 57

in NAND, such as data center appli-
cations. Many new developments in
NAND applications have been reported
at the ISSCC and Flash Memory Sum-
mit (FMS) every year, and this article
references many presentations from
those conferences.

3D NAND Architectures
and Scaling
NAND flash was invented by Dr. Fujio
Masuoka from Toshiba Corporation
and was presented when he publish-
-ed his NAND flash paper at the 1987
IEEE International Electron Devices
Meeting in San Francisco [2]. Generally,
flash memory (regardless of whether
nor or NAND flash is used) stores the
data into an isolated area, such as a
floating gate, or in a charge-trapping
area. To program a cell, electrons are
forced from a substrate into the float-
ing gate by quantum jumping under
a strong electric field across an oxide
layer. To erase a cell, the reverse pro-
cess is done, with electrons pulled out
of the floating gate back to a substrate.
As the name NAND indicates, the long
string of memory cells is contacted
out with two terminals. The source
side is called the cell source, which
is commonly connected for many
NAND strings, and the drain side is
connected to the bit lines and then to
sensing circuits [3]. To use an analogy,
one NAND string is like one floor of
hotel rooms, with only one entrance
and one exit. You need to open all the
room doors on the floor to get access
to your room for entrance and exit.
This collective access of one string of
memory requires that NAND opera-
tions of read and write be done in a
systematic way. For example, read
must be done with selected cells at
read voltage and unselected cells at
high passing voltage to let the current
flow through the NAND string. Write
must be done sequentially from one
end of the string to the other. Jump-
ing out of order in word lines is not
allowed to prevent program disturb
situations. The erase function is done
by whole blocks.
In the 2D NAND era, NAND strings
were laid flat on the silicon wafers.

	

Over the years, memory cell size
shrank to 15 nm in 2012 [1]. In attempt-
ing to shrink the memory cells below
15 nm, the industry faced three major
challenges. First, with a greatly re--
duced floating-gate size, the sensitiv-
ity of losing a single electron caused
the threshold voltage (Vt) to shift
a noticeable amount. Second, with
reduced size the neighboring cells
were so close together that neighbor
interference became bad and signifi-
cant program time was consumed to
correct the neighbor interferences [4].
Third, more advanced lithography
which is quite expensive, would need
to be used. The first two factors are
the main stumbling blocks the indus-
try has encountered in continuing
to scale for 2D NAND, with attempts
causing significant reliability and per-
formance degradation [5].
In 2013, Samsung presented its
first 3D NAND at a flash memory
summit: a 24-layer, 128-Gb chip [6]
for production. This was the start of
the transition from the 2D NAND era
to the 3D NAND era. As early as 2007
[7] and 2009 [8], Toshiba (now known
as Kioxia) engineers had published
papers discussing the possibility of
making a 3D NAND called bit cost
scalable (BiCS), using two different
architectures. The 2007 architecture
was called straight-shaped bit cost
scalable (S-BiCS), a design wherein
the source lines were at the silicon sub-
strate and connected through a dedi-
cated connection. The second paper
was published in 2009, and the archi-
tecture was called pipe-shaped bit
cost scalable (P-BiCS), wherein two
NAND strings were connected in the
substrate layers, and source lines were
connected on the top metal layers. Both
designs were implemented, with some
manufacturers such as Hynix, using
the P-BiCS 3D NAND starting in 2015,
whereas others adopted the S-BiCS.
The charge-storage media was also
implemented differently among ma--
nufacturers. Although Samsung,
Hynix, and Western Digital/Kioxia
used the charge trap layers for stor-
ing electrons, Intel/Micron used
floating gates in 3D NAND. The Intel

and Micron design emphasized the
reliability of floating-gate types of
3D NAND in QLC applications [9], but
the charge-trapping 3D NAND dem-
onstrated better scalability because it
was more suited to growth in layers.
In recent years, most NAND manu-
facturers reportedly, except Intel,
converged to S-BiCS with chargetrapping technology.
Three-dimensional NAND cells
are cylindrical (or macaroni-like) in
shape, as shown in Figure 1. This has
the advantage of allowing large cell
areas compared with 2D NAND cells.
The charge-trapping area is bigger so
that large numbers of electrons can
be stored there, which overcomes
the first difficulty listed previously.
The loss of electrons from chargetrapping layers can happen only in
the vertical direction to neighbor
word lines. The cylindrical nature
of the cell-to-cell interference limits
to vertical directions, i.e., between
word lines. There is no interference
between cells on the same word
lines, which overcomes the second
difficulty discussed previously. The
dramatic reduction of cell-to-cell in--
terference in 3D NAND boosted pro-
gram performance and reliability. As
a rule of thumb, 3D NAND TLC has
similar program speed and reliabil-
ity as 2D NAND MLC, serving perfor-
mance lane products. The 3D NAND
QLC can match the program speed
and reliability of 2D NAND TLC,
which is very useful in mainstream
products or cold-storage applica-
tions. The cylindrical cell is large in
dimension to avoid the need to use
extreme ultraviolet lithography.
A cylindrical 3D NAND cell is
composed of the poly channel, tun-
neling oxide, charge-trapping lay-
ers, block layers, and metal gate [10].
Compared with 2D NAND, the poly
channel in 3D NAND has different
properties from the single crystal-
line silicon substrates. Another major
difference between 3D NAND cells
versus 2D NAND cells is the chargestorage media. In 2D NAND cells, a
poly-silicon floating gate is used to
retain charges for the cell, to keep it

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