IEEE Solid-States Circuits Magazine - Fall 2020 - 59

Physical scaling in 2D NAND is basi-
cally shrinking the cell to be small
in surface area-the xy area. Threedimensional scaling is not only in
the xy direction but also in the z
direction-growing more layers.
There are challenges as we grow
the NAND string taller, such as lon-
ger etching times and increased
cost of building the memory cells.

Memory
Array

SA /PERI

Memory Array

Memory
Array

SA /PERI

More % Area on PERI/SA
(a)
CNA

CUA (PUC)

CBA
CMOS Wafer
SA /PERI

Memory
Array

Memory
Array
SA /PERI
* 2D
* 3D

Memory
Array

Memory
Wafer

SA /PERI
* BiCS (ISSCC 2019)
* Hynix (FMS 2018)
* Micron (ISSCC 2016)

* YTMC-Xtacking
(FMS 2018)

(b)
512-Gb
Array
Plane-0

512-Gb
Array
Plane-1

Double # Planes, Double Write
Throughput
Row Decoder

NAND Reliability

per cell and 16 states. Each state
represents a Vt to which the cell is
programmed. The horizontal axis of
Figure 3 is a representation of the Vt
of each cell after programming. To
control the state distribution within
a narrow voltage range, a special
program algorithm is used to con-
trol cell by cell. This famous lockout

Memory
Array

Row Decoder

Flash Reliability and Management

Another way of scaling is logical
scaling, where the process cost is
similar but more states are put in
each cell. As shown in Figure 3, SLC
is one bit per cell, and there are two
states, erase and program. The MLC
has two bits per cell, which has four
states. TLC has three bits per cell
and eight states. QLC is four bits

Row Decoder

From a system point of view, the
benefits of the different architectures
are reflected in their write through-
put. The write throughput, a critical
performance indicator for NAND, is
determined by the amount of data,
such as 32 KB, that is programmed
all at once. In the traditional CMOSnext-to-array (CNA) architecture, the
two-plane chip architecture is preva-
lent for compact die sizes. A total of
32 KB of data can be programmed
together per chip. A four-plane archi-
tecture can also be made, but it is
about 15% more expensive due to the
extra die size needed to add more
SAs for each plane. In the CUA archi-
tecture, four planes per chip have
become the new norm because there
is basement area under the memory
array where the extra SA can be put
without an extra die size penalty
[14]. The four-plane devices have 64 KB
of data programmed together per
chip to double the write throughput
compared with the two-plane chip.
As the number of layers grows ever
higher, the array size in the xy direc-
tion will be reduced for the same
capacity, such as the 1-Tb chip. In
this case, the capacity of the die is
increased to ensure the peripheral
circuits are totally hidden under
the array.
The CBA architecture has similar
advantages as CUA in making fourplane devices without incurring die
size penalties. The CBA CMOS shrink-
age can be better than that of CUA in
general, but high-voltage transistors
and analog circuits cannot be scaled
easily like logic circuits.

Page Buffers and Column Decoder
Peripheral Circuits

Plane-2

Plane-3

BL
WL

Cell Array
(128 Gb)
Plane-1
Plane-0
Peripheral Circuits and PADS
CUA (Four Planes)

CNA (Two Planes)
(c)

FIGURE 2: (a) The peripheral circuits next to arrays. As the array grows taller with NAND scaling, the area occupied by the peripheral circuits grows percentage wise. (b) Three different
architectures. (c) A two-plane architecture in conventional [11] and a four-plane architecture in
CUA [14]. PERI: peripheral; CNA: CMOS next to array; CUA: CMOS under array; PUC: peripheral
under cell; CBA: CMOS bounded array.

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IEEE Solid-States Circuits Magazine - Fall 2020

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