algorithm was the first patent of SanDisk founders Sanjay Mehrotra and Eli Harari [16]. The cell's natural distribution com- es from cell-to-cell variations due to the cell's geometrical dimension dif- ference from process variations. If the cell is programmed without veri- fication, the natural distribution of the cell in one chip could be as large as a three-to-four-distribution width. To ensure the QLC 16-state distri- bution is within the Vt window, the final distribution must be narrowwidth for each distribution. Program algorithms are important to con- trol the cells into a confined narrow Single Memory Cell noise for the cells. Although the ini- tial threshold can be different, the cell threshold will march in a similar slope as more high-voltage pulses are applied. When cells reach the tar- geted Vt, the cells will have a lockout to prevent further programming in the subsequent program pulses. Fig- ure 4(b) shows the cell distribution on the word line moving under each pro- gram pulse [17]. The gap between the neighbor state is called the Vt margin. The Vt margin is a very important concept for NAND flash reliability. Larger Vt margins will provide higher reliabil- ity, with the neighboring cells will distribution. As shown in Figure 4(a), the program algorithm in simplified form has two parts, program pulse and program verify pulse. Each pro- gram pulse exerts a high voltage on the word line to force the electrons to jump through the tunneling oxide. After each program pulse, the cell Vt is verified to see that the cell reached the targeted threshold. The program pulse has increasing voltage level (VPGM) from one pulse to the next in a uniform staircase style to ensure the electron tunneling reaches a steady state. In the steady state, the Vt increment predictably depends on the staircase height (DVPGM) plus some SLC One Bit per Cell ER MLC Two Bits per Cell ER TLC Three Bits per Cell ER QLC Four Bits per Cell ER 1 1 2 3 3D TLC == 2D MLC 1 1 2 3 4 2 3 4 5 6 5 6 7 3D QLC == 2D TLC 7 8 9 10 11 12 13 14 15 FIGURE 3: The logical scaling of a NAND flash cell. Program Sequence Start Program Increase Program Voltage No Verify Read Are All Cells Programmed? Yes Completion (a) Erase DVPGM (b) FIGURE 4: (a) The program algorithm with program loops and (b) programming the cell from erase state to final distributions with program verify and lockout to tighten the distribution. 60 FA L L 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE