IEEE Solid-States Circuits Magazine - Fall 2020 - 61

not easily drifting into each other.
The amount of Vt margin should
be budgeted at the beginning of
the chip's life with the end of life in
mind. The end-of-life specification
is customer specific, such as a data
retention spec in terms of time at
certain temperatures or/and number
of program/erase (PE) cycles needed
to address certain applications, nor-
mally specified in SSDs as drive
write per day (DWPD) and/or write
throughput specified in megabytes
per second. Ultimately, the cell pro-
cess is the foundation of flash cell
reliability, with multilayer materials
conforming to nanometer dimen-
sions having microscopic variations.
The feedback from reliability studies
to process technology splits is impor-
tant for enhancing cell reliability, and
this enhancement process takes time
because it depends on the design of
experiments of various trials.
NAND chips are designed to trade
write performance against reliability.
Large Vt margins (i.e., good reliabil-
ity) with narrow distributions can
be achieved by programming slowly
with smaller program step sizes

and vice versa. In similar fashion,
tradeoffs between performance and
power are also done. These tradeoffs
can be performed at the NAND chip
level or at the product level. In an
SSD, there can be tens, if not hun-
dreds, of chips on one drive. Each
drive has power envelopes specified
in watts. If too much power is con-
sumed and exceeds the criteria, the
drive has to choose fewer chips oper-
ating at the same time. On the NAND
chip level, peak power can be man-
aged by staggering the operations
to nonoverlapping from die to die or
plane to plane within one chip or by
relaxing the time charging of certain
voltages with delay times to reduce
the peak power [18].
There are important aspects of
NAND reliability that we normally
define in the specifications. The
first one is data retention. The paper
analogy is a letter written on paper
that, after a long time, gets damp so
the words on the letter are hard to
decipher. In a similar way, the charges
trapped in the NAND flash cells can drift
to neighbor cells or escape the charge
trap over time. High temperatures

are worse for the cell and make it
harder to retain charge after being
programmed. Data retention speci-
fications are often defined as a
period of time at a certain tempera-
ture that the NAND can hold the
data. Data retention is the event of
losing charge, so the cell Vt thresh-
old will shift to a lower voltage for
a programmed cell. The higher Vt
states normally lose charge faster
than the lower Vt states due to high
electric fields. The Vt margin will be
reduced after data retention. In the
case of reduced Vt margin, the opti-
mum read point should be found to
ensure that the readout data have
minimum error bits. Some NAND
designs have an optimum read point
search algorithm designed [19]. As
shown in Figure 5, multiple reads (N
stage read in the figure) were done
on each state MP1, MP2, and MP3.
The optimum read level was found in
the valley between two distributions
using multiple read. Then, read was
performed using ABL read with the
optimal read point acquired. Acquir-
ing the optimum read point can be
time-consuming, which impacts the

SVTR Normal Mode (Middle-Page Read Case)
VTR

CALR
ABL Read

SBL Read
V

MP1
State

MP2
State

Data Out

MP3
State

MP1
State

MP2
State

MP3
State

N Stage Read
in One State
Selected WL
t
Bit Count

B.C.

Bit Count (First)

Vt
Optimal Read Level

FIGURE 5: The multiple read (N stage read) was done on each state: MP1, MP2, and MP3. This read can be in selected bit line (SBL) sensing
mode (SBL read). The optimum read level is found in the valley between two distributions. The read is performed using ABL read with the
optimal read point acquired. VTR: Vt tracking read; SVTR: subject VTR; WL: word line; CALR: calibrating read.

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