IEEE Solid-States Circuits Magazine - Fall 2020 - 65

a push to grow to five bits per cell
[5]. There are many new innovations
using NAND in new products every
year. The FMS, held in August annu-
ally, has become a booming event.
There are new standards coming
out, such as NVMe-oF and Ethernetconnected bunch of flash (EBOF) out
of the Open Compute Project. The
idea of using NAND in data centers
has been a hot area for innovation.
Moving compute to SSDs has gained
some momentum due to the world's
big data deluge. There are needs for
faster and lower-latency nonvolatile
memory to bridge between DRAM
and NAND or to replace DRAM with
cheaper memory. Many emerging
technology activities are trying to
fill the storage-class memory gap
[5]. Finally, it is not easy to replace
DRAM-like performance and reli-
ability with NAND-like cost. There
is still a lot of work to be done, and
a lot of new NAND products will be
created in the future for the fully
connected digital world with data
analysis and artificial intelligence.

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About the Author
Yan Li (Yan.li@wdc.com) received her
B.S. degree in modern physics from
the University of Science and Technol-
ogy of China. She received her M.S.
and Ph.D. degrees in materials science
and engineering from Lehigh Univer-
sity, Bethlehem, Pennsylvania. She is
currently a vice president for memory
design at Western Digital, leading
advanced 3D NAND design as well as
other nonvolatile memories and new
innovation initiatives. In 1998, she
joined SanDisk Corporation, Sunny-
vale, California, working on flash
memory technology. She led teams
that designed many generations of
NAND flash memory, including the
industry's first three-bits-per-cell
NAND memory, and brought them
into production. She won the Lewis
Winner Award for best paper at ISSCC
in 2008 and 2012. She also serves on
the ISSCC Machine Learning Techni-
cal Paper review committee. She has
created many innovative ideas to
improve NAND products and holds
more than 200 patents.


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