IEEE Solid-States Circuits Magazine - Fall 2020 - 71
Data
Stream
Data FIFO
0
Data FIFO, Data-Driven Channel Selector, and
1-µs Hop Mixer Controller are all in the
same block called Crytographically
Secure Pseudorandom Channel Generator.
1
1-µs Hop Mixer
Controller
Data-Driven Channel Selector
Div1
Ctrl
Div2
Ctrl
Walsh1
Ctrl
Walsh2 LPF1
Ctrl
Ctrl
LPF2
Ctrl
Quadrature
Walsh Shaper
BAW1
÷N
φhop(t )
÷2
Sideband
Mux
Polyphase Filter
PA
Time-Interleaved 1-µs FH Tx Path 1
φhop(t )
Quadrature
Walsh Shaper
BAW2
÷N
÷2
Polyphase Filter
Sideband
Mux
Time-Interleaved 1-µs FH Tx Path 2
FIGURE 8: The time-interleaved BAW-based Tx architecture with 1ns bit-level FH and data-driven random channel selection for physical-layer
security against selective jamming and data overwriting [6]. FIFO: first in, first out; PA: power amplifier; LPF: low-pass filter
depicted in Figure 11(a) along with
its key features, including the en-
tire ISM band coverage, bit-level
hopping with a 1-ns hop period,
and data-driven dynamic random
channel selection scheme. At each
microsecond, the channel is se-
lected randomly based on the user
data bit stream using the on-chip
CS pseudorandom channel genera-
tor (CS-PRCG), and then the timeinterleaved BAW-based Tx system
hops to the selected unpredictable
carrier frequency.
For the measured bit-level FH spec-
trogram illustrated in Figure 11(b),
an example data packet is formed
as a 5-bit-long preamble represented
by only bit 1s and 10-bit-long data.
As with the data bits, preamble bits
are also transmitted on randomly
selected carrier frequencies with
1-ns hop periods. The current data
bit is utilized for deciding which of
the random channels should be used
Frequency
f (0T)
Tx Path 1
f (3T)
Tx Path 2
Time Interleaving
f (4T)
f (2T)
f (1T)
f (3T)
f (0T)
f (1T)
f (2T)
f (4T)
Time
1 µs
FIGURE 9: Time interleaving enables achieving seamless 1ns bit-level FH by avoiding the
dead zone between successive data bits [6].
for data transmission. In every hop
period, two randomly selected chan-
nels for bit 1 and bit 0 are designat-
ed. For instance, Ch31 is designated
for bit 0 and Ch14 for bit 1 in the
first 1-ns hop period; since the first
bit is a preamble bit of 1, the Tx hops
to 2.414 GHz (Ch14). The next bit, an-
other preamble bit of 1, determines
the next carrier frequency of 2.437 GHz,
Ch37, as highlighted in the top part
of Figure 11(b). In addition, the use
IEEE SOLID-STATE CIRCUITS MAGAZINE
FA L L 2 0 2 0
71
IEEE Solid-States Circuits Magazine - Fall 2020
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2020
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