IEEE Solid-States Circuits Magazine - Fall 2020 - 8

TH E ANALOG M IN D

Behzad Razavi

The Design of a Comparator

Nyquist-rate and oversampling analog-to-digital converters (ADCs) incorporate comparators to perform
quantization and possibly sampling.
Comparators thus have a significant
impact on the speed and precision
of ADCs. This article presents the
step-by-step design of a comparator and the discovery of its various
trade-offs.

General Considerations
A comparator senses a differential
input and generates a logical output
according to the polarity of the input
difference. In an ADC environment,
we are interested in the following
comparator design parameters: input offset, speed, power consumption, metastability, kickback noise,
and input-referred electronic noise.
The design begins with the selection
of target values for some of these parameters. Here, we aim for an input
offset lower than 5 mV; a clock rate,
fCK, of 5 GHz; and a power consumption of 1 mW. After the design meets
these requirements, we examine the
remaining parameters and decide
whether they are adequate.
For this article, we selected the
StrongArm latch as the comparator
core. Readers are referred to [1]-[4]
for the properties and operation details of the circuit. Shown in Figure
1, this topology offers several desirable attributes: it requires a singleclock phase; draws no static power;
exhibits an input offset that arises
primarily from the input pair, M1

the ground after the comparator has
made a decision. The circuit's power
consumption in the signal path is
2
[4].
given by 2fCK C P V 2DD + fCK C X V DD
Additionally, the clock path draws a
power of fCK C CK V 2DD, where CCK is the
sum of the gate capacitances of M7
and the four PMOS switches, S1-S 4.
T he precha rge action in the
StrongArm latch offers two benefits.
First, it enables VP and VQ in Figure 1
to begin from VDD, thus keeping M1
and M2 in saturation for some time.
This allows the input transistors
to provide gain. Second, after each
comparison, the four internal nodes
recover from the states developed
on them and are " equalized. " This
ensures that the states in one clock
cycle are not inherited by the next,
suppressing " dynamic " offsets. As
depicted in Figure 2, if, at the end
of the precharge mode, VP and VQ do
not become exactly equal and bear a
difference of DV, the subsequent amplification mode begins with such a
difference stored on CP and CQ , suffering from offset.

and M2; and delivers rail-to-rail output swings [4].
A brief overview of the StrongArm latch's operation proves helpful
here. As explained in [4], the circuit
of Figure 1 begins by precharging
nodes P, Q, X, and Y to VDD. We denote
the capacitances at these nodes by
C P , C Q , C X , and CY, respectively, and
assume that C P = C Q and C X = C Y .
When CK goes high, M1 and M2 act
as a differential pair with capacitive
loads, and VP and VQ fall from VDD
while yielding a differential component proportional to Vin1 - Vin2 . This
mode continues until VP and VQ drop
to roughly VDD - VTH3,4, creating a
voltage gain approximately equal to
2g m1, 2 VTH3,4 /I SS, where g m1, 2 denotes
the transconductance of M1 and M2,
and I SS is the tail current [3]. At the
end of this mode, M3 and M4 turn
on, causing VX and V Y to fall until M5
and M 6 are activated. One output is
then pulled back to VDD by M5 or M 6
while the other falls to zero. As examined in [4], the role of M3 and M4
is to cut the current path from VDD to

VDD
CK

M5
S1

S3
X

Vout

M3
Vin1

Q
M1

VDD-VTH5,6

FA L L 2 0 2 0

FIGURE 1: The StrongArm latch and its waveforms.

IEEE SOLID-STATE CIRCUITS MAGAZINE

VQ
VX

Vin2

Digital Object Identifier 10.1109/MSSC.2020.3021865
Date of current version: 18 November 2020

VP
VDD

IEEE Solid-States Circuits Magazine - Fall 2020

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2020