IEEE Solid-States Circuits Magazine - Fall 2020 - 80

It is well understood that in recent process
nodes, technology complexity has been driving
significant challenges in circuit performance as
well as robustness.
Why Is Reliability a Problem Today?
It is well understood that, in recent
process nodes, technology complex-
ity has been driving significant chal-
lenges in circuit performance as well
as robustness [3]-[5]. Less mature
manufacturing processes lead to less
robust models at design time. In addi-
tion, geometric scaling and restrictive
design rules have caused a degradation
in reliability characteristics.
Issues that result in systematic or ran-
dom variation at time zero (i.e., design
issues) can often (though not always) be
identified and screened out. Burn-in tests
screen out latent defects to eliminate
infant mortality [6] (see the standard

bathtub curve, Figure 1), and reliability
mechanisms like latch-up and electrical
overstress (EOS) are included as part of
the standard product qualification. For
time-emergent issues, however, units
can only be selectively sampled and
aged to predict postlife performance. In
addition, there is no good way to screen
wear-out effects like electromigration.
Devices thus need to be " correct-by-con-
struction, " as far as aging effects go, so
as not to fail catastrophically during the
useful lifetime. It must also be ensured
that the wear-out regime is outside of
the useful life of the product.
Market segments that require prod-
ucts to function for longer lifetimes, or

What Is Reliability?
Reliability, as used here, is the ability of a circuit to meet its specifications within a target defect
rate under specified conditions over a given period of time [1]. A designed circuit can be " unreliable " [2] due to spatial as well as temporal effects. This article primarily considers effects that
vary transistor parameters as a function of time and cause circuit performance to degrade [S1],
as opposed to built-in, fabrication-driven variation effects.

Reference
[s1] C. G. Shirley, " A defect model of reliability, " in Proc. 33rd Annu. Int. Reliability Symp., Las Vegas,
NV, Apr. 3, 1995, pp. 3.1-3.56.

to operate under more stringent condi-
tions, add a further layer of complexity
to design for reliability. An example is
a field-programmable gate array/pro-
grammable logic device market seg-
ment, with lifetimes close to 15 years
[7]. Another is a design that meets the
functional safety requirements for
automotive or safety applications [8].
In analog design, an additional
complexity is that there are numer-
ous postdegradation metrics, from
offset and linearity to jitter and dutycycle degradation. This makes deal-
ing with reliability mechanisms a
greater challenge.
All of these challenges impose the
requirement of a robust simulation
methodology to predict the functional
and performance degradation of cir-
cuits during the pre-silicon phase. A
large amount of work has been accom-
plished in this area, and transistor and
interconnect models, as well as simula-
tion methodologies, do offer a reason-
able prediction of aging and reliability
in circuits today [5], [9]-[11].
Even with available simulation
capabilities, the number of reliability
effects that need to be simulated, ana-
lyzed, and accounted for make a post-
design " simulate and fix " approach
time-consuming, iterative, and costly.
This article thus gathers and presents
design strategies that can be incor-
porated in analog circuits to address
these issues and so result in a clean
reliability design with fewer iterations.

Common Reliability Challenges
and Mitigation Techniques in
CMOS Circuits

Failure Rate

Infant Mortality

Wearout

Useful Lifetime of
Product

Time
FIGURE 1: The bathtub curve: failure rate over product lifetime.

FA L L 2 0 2 0

IEEE SOLID-STATE CIRCUITS MAGAZINE

This section discusses several issues
that currently need to be accounted
for in CMOS circuits. While this is
not a comprehensive list, it covers
the important mechanisms that can
significantly impact the design of
the circuit.

Time-Dependent Dielectric
Breakdown
Time-dependent dielectric breakdown
(TDDB), [1] refers to the breakdown
that occurs due to strong vertical
electric fields across the gate oxide.

IEEE Solid-States Circuits Magazine - Fall 2020

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