IEEE Solid-States Circuits Magazine - Fall 2020 - 81

The increased electric field gener-
ates traps and can result either in
an open or a short that causes a
gate-leakage current (stress-induced
leakage current).
TDDB is primarily voltage and
stress time dependent, with higher
voltages close to the device's Vmax
from gate to drain, source, or bulk
and longer exposure times caus-
ing a greater defects-per-million
impact. In digital circuits, this mani-
fests as performance or VCC Min
degradation [12], [23].
The typical approach to handle
TDDB is that of relying on electrical
checks to ensure that all transistor
nodes in the schematics and layouts
meet the defined limits. Dynamic
EOS simulators check whether the
limits are met during transient
operations. In addition, variation
in channel and gate currents with
higher gate voltages needs to be cor-
rectly modeled in the technology
file to verify its impacts on circuit
performance [9]-[11].
From a circuit perspective, the
impact of TDDB can be potentially
managed by choosing lower supply
voltages, if feasible. Stacked topolo-
gies, which are used to reduce HCI
effects, can also reduce the differen-
tial to the gate and help with TDDB.
Techniques such as slowing down
slew rates as well as schemes such
as power gating reduce the circuit's
exposure time to high voltages, thus
limiting degradation.
Another way to prevent TDDB is
to avoid having undriven nodes in
the circuit that can get charged by
capacitive coupling, causing a volt-
age differential to the gate. Weak,
stacked, and undriven nodes are sus-
ceptible to undershoots, and, given
other concerns with floating nodes, it
is wise to have electrical rule checks
that identify these in the circuits and
to add " leakers " where necessary, as
depicted in Figure 2.

All of these challenges impose the requirement
of a robust simulation methodology to predict
the functional and performance degradation of
circuits during the pre-silicon phase.
(drain to source) can cause the forma-
tion of electron-hole pairs through
impact ionization. These carriers go
into the gate, causing transistor degra-
dation [13]. HCI manifests as a thresh-
old voltage shift, and lower mobility
and transconductance and can be
evaluated by simulations, as long as
degradation of transistor performance
due to aging is modeled.
In digital and clocking circuits,
hot carrier effects occur during tran-
sistor switching. This implies that
faster clock frequencies and, in gen-
eral, slower slew rates/higher loads
cause more HCI degradation. The
degradation is usually accounted
for by budgeting in the timing mar-
gin. In analog circuits, high-channel
power for extended periods of time
is the key predictor of HCI failure,
particularly in high-voltage, stacked
circuits. Here, as well, designs are
simulated to meet post-aging perfor-
mance-meaning that a guard band
is applied during the design process,
depending on the metric of interest.

inp

One area of focus in managing
HCI degradation in analog circuits is
controlling device voltages [drain to
source (Vds)]. This can be achieved
by stacking, or adding diode devices
to limit Vds, as illustrated in Fig-
ure 3(a). Figure 3(b) shows a scheme
to manage Vds by controlling the
power supply to the circuit and keep-
ing it sufficiently low. In addition,
the device current should be man-
aged appropriately: reducing voltage
across the gate and source terminals
(Vgs) and adding devices in parallel
to get back to the same total current
can be a useful technique.
Techniques used to limit the pro-
cess and spatial variation can also
be used to manage HCI; for instance,
using trimming across the process
skew can prevent overall variation,
including aging. In addition, the
strategies described for TDDB are
largely applicable to HCI mitigation
as well: active power gating wherever
possible and mitigation of undriven
nodes in the design.

inn
Tail
Coupling
Before Fix

clk

Disable
Enable

After Fix

HCI
In short-channel transistors, when
the channel is on and a current is
flowing, a large lateral electric field

FIGURE 2: Handling undriven nodes: clock gate " clk " or discharge " tail. "

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IEEE Solid-States Circuits Magazine - Fall 2020

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