IEEE Solid-States Circuits Magazine - Fall 2020 - 83

Refclock
PLL

Clock
Divider

VCO
When the reference clock is not detected,
override VCO bias voltage from RDAC to
send the low-frequency, clock-protect VCO,
divider, and clock distribution from BTI aging.

Refclock Not
Detected

Clock
Distribution

Switch to a high
divide ratio when
refclock is not detected
to keep the clock
frequency for
mitigation low.

Timing Path of
Interest-Half
Cycle Paths

Sending the clock through VCO, divider, and clock
distribution instead of parking them in static state
prevents duty-cycle degradation due to BTI in all
three components. This allows half-cycle path
timing to be met at the destination post aging.

FIGURE 4: BTI clock mitigation when the reference clock to the phase-locked loop (PLL) is not detected. RDAC: resistive digital-to-analog
converter.

on the duty-cycle variation, can also be
leveraged [17].
Circuits with complementary in-
-
puts that stay in one direction over
the lifetime, such as comparators or
level shifters, are also particularly
susceptible to BTI effects [2]. In par-
ticular, offset voltages are impacted
in comparators that are parked in
one direction (see Figure 5). The com-
parator device flavor should thus be
chosen to minimize BTI severity. Off-
set cancelation schemes [18], used
to mitigate the offset across process
variation, can be used to reduce the
overall offset voltage variation.

Interconnect Effects-
Electromigration/Self-Heat/
Localized Thermal Effects
The reliability of interconnects is
another problem in contemporary
circuit design. Electromigration is
created by a net current that causes
atoms to migrate and resistance to
increase, resulting in both opens and
shorts. Self-heat is a local effect result-
ing from the currents on an intercon-
nect. Due to the transistor structures
in fin field-effect transistor (FinFET)
devices, resulting in lack of lateral
access to the bulk, self-heat effects
are higher, creating higher local tem-
peratures [19], [20]. This phenomenon
in FinFET processes results in device
temperature limits, in addition to
interconnect limits, and is referred as
a localized thermal effect (LTE) [21].
As discussed previously, ele-
vated temperature generally makes
dev ice ag ing more severe, a nd

hence, these interconnected reliabil-
ity effects could lead to accelerated
aging effects. Most efforts around
design for interconnect effects cen-
ter on layout techniques. Designs
using degradation-aware cell librar-
ies [22], careful floor planning [21]
keeping current paths in mind, and
proper layout techniques-building
robust power grids and using wide
enough metals and via structures to
dissipate heat-all help ensure tol-
erance to these effects. In addition,
devices can be placed with multiple
legs to support the required cur-
rents, adding dummies as needed
(see Figure 6).
Another design aspect to be consid-
ered for managing LTE is to carefully
mitigate dc and contention-current

paths. A particular risk could occur
during power up and power down
or while ungating power gates and
power multiplexers. An example of
addressing this risk would be with
staggered ungating or as in Figure 7,
where delays ensure lack of conten-
tion, thus reducing reliability risk.

Design Techniques for Reliability
Following is a summary of the design
techniques discussed in this article.
1) Use low-voltage design when
possible.
2) Apply standard design practic-
es, such as good slopes and low
fanout on logic paths.
3) Employ power gating when pos-
sible, limiting activity factors and
currents of high-performance

VCC
MP3
Vs
IN-
0.5 V

MP1

MP2

With large signal-differential
inputs, (Vin- - Vin+) can modulate
IN+ Vsource (Vs) Altering Vs affects
1 V the difference of VgsP1 versus VgsP2,
affecting BTI degradation
between MP1 versus MP2 and thus
Output altering the achieved post-aging offset.
In this example, swapping the inputs,
with 1 V being high enough to
increase Vs, causes more even
degradation across the two devices
and lower post-aging offset voltage.

FIGURE 5: Comparators are susceptible to offset voltage degradation due to BTI.

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 2 0

IEEE Solid-States Circuits Magazine - Fall 2020

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2020