nbias Single Leg Device All five are active device legs sourcing the current, leading to an increase in the temperature overtime. D nbias Width = 5x S To PMOS Current Source D/S S D/S D/S D/S Width = x Total W = 5x D To PMOS Current Source VSS VSS S D/S D S D Dummy nbias Dummy Five active device legs sourcing the current, interlaced with dummies to lower temperature. S D/S D Width = x Total W = 5x To PMOS Current Source VSS FIGURE 6: Devices placed with dummies to support required currents. S: source; D: drain. Power Mux VCC1 VCCOUT1 VCC2 Delays to make sure nodes are undriven before being discharged to ensure no contention and electromigration risk. VCC1 VCC2 Power Mux VCC1 VCC2 Delayed Pull Down VCC2 VCC1 Delayed Pull Down FIGURE 7: Ensuring the lack of contention to mitigate electromigration risk. 84 FA L L 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE VCCOUT2 paths like clock networks and dc paths. 4) Carefully manage dc and con- tention currents in the design. 5) Manage Vds across devices by adding stacking or diodes in-be- tween as needed. 6) Discharge undriven nodes in the design. 7) Utilize analysis-based device choice on unbalanced designs like comparators. 8) Use low-frequency BTI clocking to avoid long-term static parking of the clock network and receivers. 9) Apply trimming techniques to control currents across process skews, temperatures, and volt- ages and other techniques that control overall variation, such as duty-cycle correction, chop- ping, and offset cancelation. 10) Design using degradation-aware standard cells, careful floor-plan- ning, and layout for reliability verification.