IEEE Solid-States Circuits Magazine - Fall 2020 - 85

The preemptive use of these strate-
gies can result in a design that is easier
to close from a reliability standpoint,
thus saving design cycles in iterating
through and cleaning up reliability
flows. Ultimately, it reduces the fail-
ure rate and improves the long-term
performance of the design.

Acknowledgments
We would like to acknowledge our
team for the contributions and learn-
ing, particularly Ping Xiao and Kow-
shik Gandham for some of the example
circuits. We would also like to thank
David Smith, Kaushik Chanda, Binta
Patel, Nasser Kurd, and Mark Neiden-
gard for the review and feedback and
for sharing their knowledge.
References

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About the Authors
Maneesha Yellepeddi (maneesha
.yellepeddi@intel.com) received her

B.E. Hons. degree in electrical and
electronics engineering from Birla
Institute of Technolog y and Sci-
ence, Pilani, India, in 2003 and her
M.S. degree in electrical engineering
from Oregon State University, Corval-
lis, Oregon, in 2005. That year, she
joined Intel, Austin, Texas, where
she is currently an analog engineer-
ing manager in Intel's Programma-
ble Solutions Group. She has been
involved in the design of various ana-
log circuits, including phase-locked
loops, delay-locked loops, bandgaps,
regulators, analog-to-digital convert-
ers/digital-analog converters, input-
output design for the embedded,
multidie interconnect bridge, and
so forth.
Aditya Kelkar (aditya.s.kelkar@
intel.com) received his B.E. in elec-
tronics engineering from Pune Uni-
versity, Maharashtra, India, in 2007
and his M.S. in electrical engineering
from San Jose State University, Cali-
fornia, specializing in analog circuit
design with emphasis on sigma delta
modulators. He joined Intel, Austin,
Texas, in 2011 and has worked as a
part of several Intel groups, focus-
ing on the Atom CPU/system on chip
and modems; most recently, he is
working in the Programmable Solu-
tions Group. He currently manages
an analog design team, and his inter-
ests include low-drop-out regulators,
bandgaps, and analog-to-digital/digi-
tal-to-analog converter designs.
Jeffrey Waldrip (jeff.waldrip@intel
.com) received his B.S. degree in com-
puter engineering from Mississippi
State University in 1996 and his M.S.
degree in electrical engineering from
the University of Texas at Austin in
2009. He is an analog engineer in
the Programmable Solutions Group
at Intel, Hillsboro, Oregon. Since
joining Intel in 2008, he has primar-
ily focused on phase-locked loop
(PLL) design and clocking. Previously,
he worked at Cypress Semiconduc-
tor and Freescale, developing PLLs,
high-speed serial input-output (I/O),
general purpose I/O, static RAM, and
double data rate.


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