IEEE Solid-States Circuits Magazine - Fall 2020 - 91

n for integrated transformers are in
the range of 0.5 to 2. For any given
technology, there is no fundamental
reason why a transformer should
have a lower quality factor than an
inductor. However, there are some
exceptions. For example, imple-
menting one coil in a thinner metal
(as, possibly, in the stacked layout)
will decrease its quality factor. Like-
wise, if the layout requires the use of
lower (and much thinner) metals to
implement many underpasses, the
quality factor of the device will also
be impaired.
In summary, in integrated pro-
cesses high-permeability materials
are typically not available, which
implies that a large die area is
needed to implement inductors and
transformers. The self and mutual
inductances depend on the device
geometry, and, in particular, the
mutual inductance depends on the
area of the smaller of the coupled
coils. This results in a limited mag-
netic coupling for integrated trans-
formers. The quality factor increases
(although weakly) with the inductance
value for small inductors. However,
the use of large inductors is limited
by substrate losses and by the selfresonance frequency. Furthermore,
skin effect, current crowding, and
substrate coupling limit the quality
factor of coils at higher frequencies.
Since, as discussed, it is not possible
to effectively couple inductors with
very different inductance values,
there is a limitation on the achievable
turn ratio values.

Baluns, Couplers, and Artificial
Transmission Lines

a bias voltage at the balanced port,
taking advantage of the galvanic
isolation between the primary and
secondary coils.
One issue that arises when using
a magnetic transformer as a balun is
that, in an integrated implementation,
the magnetizing and leakage induc-
tances are, as discussed, never neg-
ligible. The question is how to cope
with these parasitic elements. Since
we cannot get rid of them, we can try
and embed them in our design, using
them to our advantage. One example
of such a technique is displayed in
Figure 8, where the balun is part of
the input network of an inductively
degenerated CMOS low-noise ampli-
fier (LNA). It is well known that the
impedance looking into the gate ter-
minals of M 1 and M 2 is equivalent to
a series resistor, inductor, capacitor
(RLC) resonator [16]. If we represent
the coupled inductors of the balun
using the equivalent circuit in Figure 3(b)
and add a capacitor (C 1 in Figure 8),
we observe that the LNA input net-
work makes up a two-section ladder

As a first example of the use of a mag-
netic transformer in an integrated
circuit, we discuss its application as
a balun, that is, a device to realize
a single-ended to differential signal
conversion (or vice versa) [16], [20],
[21]. The arrangement is presented in
Figure 7. One winding of the trans-
former has a grounded terminal,
accommodating the single-ended
signal. The other winding is divided
into two subcoils (L 2 and L 3 in Fig-
ure 7) by a center tap. The structure
can be analyzed by extending (7) and
(8) to accommodate the third electri-
cal port in Figure 7. In this way, it is
straightforward to show that, if L 2 =
L 3 and k 12 = k 13 , the port at the sec-
ondary winding is a balanced port,
that is, Vdm = V2 + V3 and I 2 = I 3 ,
without any common-mode ac signal
and regardless of the termination
at the center tap. Clearly, to achieve
this condition, a highly symmetric
layout is essential. Note that the
center tap can be used to provide

Balanced Port
k12
l1
+
V1
-

L1

k13

l2

L2

Vct

L3

+
V2
-
+
V3
- l3

k

l1

+

+
V1
-

L1

k

l2

L2
Vct
L2

If L2 = L3
and k12 = k13

Vdm
-

l2

FIGURE 7: The magnetic transformer used as a balun.

Explicit Cap +
Pad Parasitics
1:nk
Zin

Zin

M 1 M2

Vin

k
C1

L1

L2

Ls /2
Vbias

C1

Ls /2

Cgs/2

(1-k 2)L2/2
L1

Ls
ωT Ls

Two-Section
Ladder
(1-k 2)L2/2

FIGURE 8: An example of the embedding of a transformer's parasitics in a ladder network.

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IEEE Solid-States Circuits Magazine - Fall 2020

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