IEEE Solid-States Circuits Magazine - Fall 2021 - 10

point here is that, to create maximum
boost at
f ,Nyq
the pole frequ -
ency should be chosen well below
this frequency. For example, to obtain
|(
Hj fK indicates
that p~ must be chosen according to
2095
=
r Nyq)| ., (7)
~ =
p
.
0952
0 312 2r Nyq
1
.( )
-
f
.
cm+
gR
1
from .( )f0392 Nyqr
mS
2
For a boost factor of 2 to 3, p~ ranges
to .( ),f0352 Nyqr
i.e., the pole frequency should be
roughly 2.5 to 3 times less than
f .Nyq
CTLE Design
CTLE design proceeds in four steps.
1) We place the degeneration pole
around one-third of fNyq
2
(8)
realize a programmable boost factor.
We can then design the DFE and
study the performance of the overall
equalizer.
We begin the design of our twostage
CTLE with a power budget of
5 mW, leaving the other 5 mW for the
DFE. Biased at 2.5 mW, each stage
then allows a current of 1.25 mA
per transistor. We then select the
as pect ratio, W/L, of M1
and M2
in
and implement
the CTLE. 2) We precede the
CTLE with the channel and examine
the flatness of the cascade response.
3) We study and optimize the eye
diagram at the CTLE output. 4) We
Figure 4(a) according to two requirements,
namely, the desired transconductance
and an acceptable
gate-source overdrive voltage. The
former plays a role in the boost factor
while the latter determines the
voltage headroom for the tail current
sources and across the drain
resistors. According to simulations, a
W/L of 10
nm /30 nm gives a gm
+=
10 mS and an overdrive of 170 mV,
both reasonable values. We then target
a boost factor of /,gR
obtaining R 400X . We also place
~ p at ()/2283 and arrive at a
value of 150 fF for CS
12 3mS
S =
r GHz
. The drain resis|H(jω)|
gmRD
tors
are constrained by the voltage
headroom; we select R 400
D =
~2.5 dB
X for
a voltage drop of 500 mV.
Figure 7(a) depicts the design
ωz ωp
ω
FIGURE 6: An illustration of an actual CTLE
response.
of the first stage. We load the circuit
by an identical stage for now.
Figure 7(b) plots the response with
LD
= 0 and LD
= 600 pH, suggesting
that inductive peaking raises the
boost from 5.4 to 6.2 dB and its corresponding
frequency from 15 GHz
to approximately 20 GHz. The dc
gain is about unity. The bandwidth
falls short of f
q =
Ny 28GHz and can
be increased by lowering RD but at
the cost of dc gain. This tradeoff
must eventually be studied when
the CTLE-DFE chain is formed.
We now cascade two such stages
so as to raise the boost factor [see
Figure 8(a)]. As an approximation
of the input ca pacitance of the
next stage, two NMOS devices with
//
WL 10 30mn=
nm are attached
to the output nodes. Plotted in
Fig ure 8(b), the overall res ponse
exhibits a boost of 14 dB at 25 GHz.
Preceding the CTLE with the channel
yields the behavior in Figure 8(c) and
hence, roughly 8 dB of loss at
f .Nyq
of
Unlike the first stage, the second
does not see Miller capacitance
multiplication, thus achieving a
wider bandwidth.
The next step is to study the eye
diagrams. Depicted in Figure 9(a)
and (b) are the channel and CTLE
outputs, respectively. We observe a vertical
opening of 250 mV and a horizontal
opening of 13 ps.
As mentioned previously, the
tradeoff between the dc gain and the
boost factor should be examined in
a given design. Specifically, does the
vertical eye opening in Figure 9(b)
increase if the dc gain is raised and
the boost is, inevitably, reduced? For
example, we can choose R 300
S =
S =
X
and C 200 fF. But simulations
LD
VDD
LD
400 Ω
Vin
M1 M2
1.25 mA
400 Ω
150 fF
1.25 mA
10 µm
W
L
=
30 nm
(a)
FIGURE 7: (a) The design of the first CTLE stage and (b) its frequency response.
10
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
400 Ω
-2
-1
1
2
3
4
5
6
108
LD = 0
LD = 600 pH
109
1010
Frequency (Hz)
(b)
1011
Magnitude (dB)
IEEE Solid-States Circuits Magazine - Fall 2021

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