IEEE Solid-States Circuits Magazine - Fall 2021 - 129

As sermo-soc is intended to be
used as a test vehicle for ongoing
research in our Motor Control
Group, the CIC datapath is designed
as a programmable filter array
(PFA), where all of the aforementioned
parameters are programmable
and reconfigurable through
a memory-mapped region on the
Wishbone interface, as shown in
Figure 7. Essentially, each PFA consists
of 11 CIC64 blocks, controlled
by a controller (CICcon). Each CIC64
block is composed of eight CIC8
blocks that can be cascaded to
form wider CIC16, CIC32, and CIC64
stages, which can be chained to
form a CIC datapath. Each CIC block
can be configured as an integrator
or a differentiator. With 11 stages,
a 64-bit sinc-5 filter can be implemented
with each of the eight PFAs.
CICcon provides a novel methodology
to implement user-defined
sequencers for the intended filter
responses. A Matlab Toolbox is
under development that will automatically
generate these configurations
in the form of a C/C++ header
file that will be compiled with the
firmware. Alternatively, it will provide
support to dynamically configure
PFAs through a USB/universal
asynchronous receiver-transmitter
(UART) interface for design space
exploration.
Trigonometry Accelerators
The vector control of ac motors
requires (inverse) Park transforms
on phase currents and voltages,
between the (stationary) frame and
the direct-quadrature frame, rotating
at a synchronous speed. These
transforms require trigonometric
(sine/cosine) calculations.
In
sermo-soc, two instances of CORDIC
engines are provided as a blackbox.
CORDIC is borrowed from École polytechnique
fédérale de Lausanne's
CORE benchmark suite and provides
25-bit fixed-point precision, from
a 24-bit normalized angle input.
The two instances are attached to
the LA bus of the Caravel harness;
therefore, they are implemented as
a combinational logic circuit whose
delay is empirically calculated and
hard-coded in the firmware.
SoC Design With
Open Source Tooling
Sermo-soc is designed with open
source tooling from concept to RTL
to GDSII. The logic design is written
in the domain-specific language
Chisel, which leverages the excellent
imperative and declarative
language features of Scala, a Java
virtual machine language. Both the
Chisel generator and emitted RTL
of sermo-soc are open sourced and
are showcased at UET's Department
of Electrical Engineering GitHub
codebank (https://github.com/ee-uet).
Openlane flow is employed as a part
of the Efabless multi-project wafer
run 2 effort, which stitches together
the Yosys hardware description
language compiler, ABC optimizer,
OpenRoad Place and Route, and
Magic back end of line tools to make
a free and open source software
(FOSS) RTL2GDSII. This experience
has greatly helped in evaluating the
quality of chip designs and the limitations
of open source tooling in the
current state, e.g., in floorplanning,
which was done with custom scripts
in Python. A GUI-based floorplanner
is also conceived and under development
that will greatly augment
this FOSS IC design initiative.
-T. Mahmood, M. Tahir, U. Shahid,
U. U. Fayyaz, and M. Kamran
Department of Electrical Engineering,
University of Engineering
and Technology, Lahore, Pakistan
Collection of EAMTA 2021
Student Projects
Teaching microelectronics has always
been a challenge: the fabrication
costs of the standard CMOS processes
and their associated design
software discourage students (and
teachers) from facing IC-related
projects. To attend to this need and
form future professionals for the
IC industry in the region, EAMTA
(https://sites.google.com/view/congresoargentinoelectronica/eamta
-2021)
was created. It is a one-week
school where undergraduate and
graduate students attend intensive
courses on topics related to micro/
nanoelectronics. The main goal of
the school is to disseminate microelectronics
knowledge and promote
the development of related technology
in the country and the region.
The academic offerings include
basic courses, where students are
introduced to the design of ICs, to
advanced courses in several different
areas, such as advanced analogic
design and digital design, among
others. The attendees also benefit
from open lectures by distinguished
academics and paper presentations
because embedded in the school
there is an international conference
in which full papers are published in
IEEE Xplore.
As a motivational booster for
the participants of the school, the
designs developed in the basic
courses are sent to fabrication on
the CMOS process available at each
specific event. This year, designs
from two courses have been sent for
fabrication on the SkyWater SKY130
process, using the Google SkyWater
130-nm open source PDK and open
source EDA tools. The Basic Very
Large-Scale Integration (VLSI) course
provides the students with knowledge
of the physical fundamentals of
MOS device operation as well as the
fundamental principles of the CMOS
microfabrication process. It also
enables them to design basic analog
and digital circuits and use CAD
tools. Students with basically no
experience in application-specified
IC design end up conceiving, designing,
and simulating a 4-bit counter.
In Figure 8, the final layouts of four
projects are shown.
In the Analog Design course, students
arrive with basic VLSI design
knowledge from other editions of the
school or from their undergraduate
courses and acquire the basic theoretical
and practical tools for the
design of analog ICs. The techniques
discussed in the course provide a
basis for the design of amplifiers on
CMOS processes. In the final project,
the students design a two-stage
operational amplifier. The finished
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
129
https://www.github.com/ee-uet https://sites.google.com/view/congresoargentinoelectronica/eamta-2021 https://sites.google.com/view/congresoargentinoelectronica/eamta-2021 https://sites.google.com/view/congresoargentinoelectronica/eamta-2021
IEEE Solid-States Circuits Magazine - Fall 2021

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