IEEE Solid-States Circuits Magazine - Fall 2021 - 17

factor for resistors; for s /12Some
smart
person or
persons
in distant
antiquity-
perhaps as far
back as the
ancient Mayans-
envisioned a
creative solution
to the tyranny
of the dominant
pole.
impact of all the poles and zeros to
overlap and cancel one another out
when in close quarters. As you push
the time constants closer together,
the ripple in the phase response
smooths out, but the end effects get
worse, and eventually the network
cancels itself out completely as a
pile of coincident poles and zeros.
You can see this effect on the orange
trace in Figure 2. The phase ripple
of the tightly packed singularities
is completely gone, but if you look
closely, the phase doesn't even make
it to -45º.
Examples of various pole-zero
patterns are presented in Figure 3.
These make sense if you think about
approaching the network from a
low frequency. The first singularity
you encounter-say, a pole-begins
to lower the magnitude on the Bode
plot and decrease the phase. However,
before the full effect of the
first singularity is felt, you encounter
the second-a zero, in this case-
which effectively neutralizes the
first pole and begins to level the
Bode plot back out. The greater the
frequency spacing of the singularities,
the more each one contributes
to the slope and phase change before
being overwhelmed by the next one.
Reputable scholars (a club to which
I don't belong) offer the ladder network
in Figure 4(a) as a way to implement
the repetitive singularities with real
components [1], [2]. Because we live
in the log frequency domain, each
component is a scaled version of its
neighbor (a is the scaling factor for
the capacitors, and b is the scaling
S+1/2
S-1/2
S-1/3
S-2/3
, ab ).= The
ladder circuit in Figure 4(a) is invariably
presented as an infinite network to
avoid the embarrassment of end effects.
However, many professionals have
stopped using infinite networks in their
designs because the constructs take up
too much die area. So, Figure 4(a) shows
a truncated version of the ladder in all
its imperfect glory.
De-Q! De-Q!
Now that you've got your head around
the idea of a fractional pole, let's put
110
100
Log Frequency
FIGURE 3: Pole and zero patterns for fractional pole and fractional zero approximations.
20
40
60
80
-20
-40
-60
-80
-100
-120
-140
C
R
C∗α
R∗β
C∗α2 C∗α3
R∗β2
R∗β3
C∗α4
(a)
-
1 mHz
1 Hz
1 KHz
(b)
FIGURE 4: A practical implementation of a square-root-of-s network showing the magnitude
(a) and phase (b) of the inset in Figure 4(a).
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
17
1 MHz
1 GHz
-15
-30
-45
-60
-75
-90
-105
Impedance Magnitude (dB)
Impedance Phase (°)
(°)

IEEE Solid-States Circuits Magazine - Fall 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2021

Contents
IEEE Solid-States Circuits Magazine - Fall 2021 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2021 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2021 - Contents
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