IEEE Solid-States Circuits Magazine - Fall 2021 - 19

it to work. We'll start by making a
half zero. And we'll choose a topic
about as far from op-amps as you
can get: power supply wiring.
Above a few tens of megahertz, the
natural inductance of supply routing
and package parasitics renders boardlevel
power supply decoupling and
bypass capacitors ineffective. So, onchip
(meaning on-silicon, in this case)
capacitors are required to keep the
supply clean and the impedance low.
But these capacitors may conspire to
resonate with the very supply inductance
they are intended to mitigate.
How to keep the on-chip capacitors
from ringing?
You need some resistance in
the mix to suppress any inductor-
capacitor (LC) tank, but where? Let's
consider your options in Figure 5.
Putting a resistor in series with the
power supply [Figure 5(b)] is never
a good idea. Increased supply im -
pedance and an activity-dependent
voltage drop are things you don't
need.
If you put the resistor in
series with the on-chip capacitor
[Figure 5(c)], it looks harmless, but
you've just shot yourself in the foot.
The resistor shuts off the capacitor
at high frequency, so there goes your
decoupling. A resistor in parallel
with the capacitor [Figure 5(d)] would
work in theory, but shorting out
the power supply with a low-value
resistor will not earn you that speedy
promotion. What if you use the
pa rallel resistor and put another
capacitor in series with it to block
the dc current [Figure 5(e)]? This
is a practical and commonly used
solution. [You may see it referred to
as a resistor-capacitor (RC) snubber.]
However, the square-root-of-s enables
us to do much better.
What's wrong with the two-capacitor
solution in Figure 5(e)? I'll let
Mr. Bode explain it to you using the
dashed lines in Figure 6(a). This
plot shows a range of inductance
that the network can safely accommodate.
You need this slack for two
reasons. First, parasitic extractors
and 3D electromagnetic simulators
are notoriously squirrely. It's hard
to get a number for the inductance
that you can trust. So, you should
pad your estimate of the inductance
with a healthy margin of error. Second,
decoupling capacitors
are often put down as " paving "
where empty space is
available. They may even
be back-annotated in the
schematic to match whatever
happened to get laid
out. In other words, you
may not know exactly
how much capacitance
you have at design
time. Planning for a range of values
makes sense.
(Note:
In this kind of impedance
plot, resonance can exist where the
inductive impedance curve crosses
the capacitive impedance curve. The
severity of the resonance depends
on how purely reactive the elements
are. In the Figure 6 example, the
Square-root-of-s
networks don't
necessarily force
an unpalatable
compromise and
can improve
performance
as well as area
efficiency.
damping resistor of the Figure 5(e),
two-cap solution puts a " flat spot "
in the capacitance curve so that
the RC network is mostly
resistive at those fre -
quencies, and resonance
will not be a problem if
an inductor im pedance
crosses there. Please see
the first column in this
series [3] for more infor -
mation about this kind of
graphical analysis. Also see
" Get the L Out! " ).
Basically, the resistive " safe zone "
happens because the damping resistor
takes the dc-blocking capacitor
out of the game at high frequencies.
This large cap is not really helping
the impedance of the supply at all. It
just blocks the dc to keep the damping
resistor from turning into a fuse.
It adds capacitance to the circuit at
100
10
0.001
0.01
0.1
1
(a)
10 KHz 100 KHz 1 MHz 10 MHz
Frequency
(b)
100 MHz 1 GHz 10 GHz
-
15
30
45
60
75
90
FIGURE 7: Simulated performance for the three-capacitor damping network in Figure 5(f) (blue
lines) and the two-capacitor network in Figure 5(e) (green lines). (a) The damping network impedance
magnitude with inductor impedance overlays. (b) The damping network impedance phase.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
19
Impedance Magnitude (Ω)
Impedance Phase (°)
L1
L2
L3

IEEE Solid-States Circuits Magazine - Fall 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2021