IEEE Solid-States Circuits Magazine - Fall 2021 - 26

the dielectric layer; the other is used
to make the connection between the
top electrode and the first metal
layer [9]. After patterning the capacitors,
the back-end-of-line process
continues in a manner identical to
a standard CMOS process. Therefore,
the integration of the Fe-caps
does not require modifications to
the standard front- or back-end proVIN
Φ1
Φ2
C1
Φ1
Φ2
Φ1
Φ1
C2
Φ2
αC2
G
= 1/3
VIN
Φ1
Φ2
C1
Φ1
Φ2
C2
Φ1
Φ2
G = 2/3
αC1
C2
Φ2 VOUT
VIN
C1
VY
αC2
VOUT
VIN
C2
αC2
FIGURE 2: The operation of the switched-capacitor converter, used in this design, with gain
settings 1/3 and 2/3 in phase 1 and phase 2, respectively [11].
C1
Phase 1
cesses, except for a slight increase in
the contact height. Also, the relatively
low thermal budget of 600 ºC for
fewer than 30 min for the fabrication
of the Fe-cap module causes no
significant shift in any of the CMOS
electrical characteristics [9], [10].
Figure 1 depicts the different types
of integrated capacitors. The efficiency
of the switched-capacitor dc-dc
converter can be maximized by using
capacitors with low bottom-plate
parasitics, and architecture that minimizes
the voltage swing across the
bottom-plate capacitors. For example,
in the case of the 1/3 gain setting in
Figure 2 based on the Dickson topology,
the parasitic capacitor C1a is
charged to VOUT in phase 1, discharged
to ground in phase 2, and vice versa
for the parasitic capacitor
aC .2
VOUT
Phase 1
VIN
C1
C2
VOUT
αC1
C1
C2
αC1
VX
VOUT
αC2
Phase 2
VOUT
Phase 2
α is
the ratio of the bottom-plate parasitic
capacitance to the charge-transfer
capacitance. Thus, the energy lost
per cycle, in this case, is CV2
a OUT
2
if
both flying capacitors are equal. In
contrast, for a 1/3 series-parallel converter
(see Figure 3), the loss due to
the bottom-plate parasitic capacitance
is approximately CV5
a OUT as the volt2
age
swing across the bottom-plate
parasitics C1a and C2a is approximately
V2 OUT
and VOUT, respectively.
In the case of a 2/3 gain setting
(see Figure 2), the parasitic capacitor
a C1
is charged to V /2OUT
in phase 1
and discharged to ground in phase
2, while C2a is charged to VOUT in
phase 1 and discharged to
V /2OUT
phase 2. It should be noted that C1a
gets charged by C2a
a
in
when the main
flying capacitors are connected back to
back. Thus, the energy lost per cycle, in
this case, is
22OUTCV /, which is lvess
VIN
Φ1
Φ2 C1
Φ1
Φ2 C2
Φ1
C3
VIN
Φ1
Φ2
Φ2
Φ2
C1 Φ1
Φ2
Φ1
αC1
Φ2
C2
Φ1
G = 2/3
VOUT
G = 1/3
VIN
Phase 1
C1
C2
VOUT
αC2
αC2
FIGURE 3: The operation of the switched-capacitor converters, utilizing a series-parallel
topology, with gain settings 1/3 and 2/3 in phase 1 and phase 2, respectively [11].
26
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
αC1
Phase 2
VOUT
C1
C2
Φ2 VOUT
VIN
Phase 1
C1
C2
C3
αC1
αC1
αC2
αC2
Phase 2
C1 C2 C3
VOUT
than the bottom-plate parasitics losses
in series-parallel switched-capacitor
dc-dc converters with 2/3 gain setting,
as shown in Figure 3. By implementing
high-efficiency switched-capacitor
dc-dc converters using Fe-caps, the efficiency
of the dc-dc converter can
be maximized.
A power management IC (PMIC) that
includes a reconfigurable switchedcapacitor
dc-dc converter has been
designed in a 130-nm CMOS process
using Fe-caps. As a proof of concept,
the chip supported gain settings of
1, 1/3, 1/2, and 2/3. The chip fabrication
was provided by Texas Instruments.
The chip micrograph is shown
in Figure 4. The PMIC achieves a peak
efficiency of 93%, including the control
circuits overhead, while supplying
500 μA, and a peak of 92% while supplying
1 mA [11], [12].
αC1
IEEE Solid-States Circuits Magazine - Fall 2021

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