30 FALL 2021 IEEE SOLID-STATE CIRCUITS MAGAZINE IFGs IFG I1 I2 I3 IIN Magnetic Core Magnetic Core Cost Size Effort Plug-In Connector Plug-In Connector BIN +- VSENSE (a) (b) BIN Slowly Varying Input BCOMP No Duty Cycling BCOMP Naive Duty Cycling BCOMP Quick Convergence BCOMP Wake Up From Last Converged Point (d) t BIN Fluxgate Sensor (e) FIGURE 7: A duty-cycled fluxgate magnetometer application and the proposed work. (a) Hall sensors in the magnetic cores with air gap are used for field amplification and stray-field rejection; (b) coreless current sensing with an array of integrated fluxgate (IFG) sensors use signal processing for stray-field rejection [21]; (c) the top view of a nonlinear IFG sensor with excitation coils drive the integrated magnetic cores into saturation, sense coils to pick up the induced voltage, and compensate for linearity; (d) the conceptual waveforms for energy-efficient duty cycling versus analog implementations; and (e) a mixed-signal architecture with a digital integrator retains last-converged compensation value during sleep and continues searching from its vicinity upon wake up [16]. SAR ADC: synthetic aperture radar analog-to-digital converter; DAC: digital-to-analog converter; SPI: serial peripheral interface; CDS: correlated double sampling; V-to-I: voltage to current. t COMP ICOMP V-to-I 12-b DAC 12 Compensation Path t EXC t t IEXC Pulse Excitation VSENSE + - SENSE Sense Path VSENSE_D + - - + + - Differential SAR ADC 9 9 Digital Integrator 13 DOUT Bandgap Reference Mode Check 2 Control State Machine (c) SPI Registers Digital BIN BEXC ICOMP BCOMP IEXC CDS