IEEE Solid-States Circuits Magazine - Fall 2021 - 37

The operational flow and timing
diagram of the proposed MACUs are
presented in Figure 18(c) and (d).
Each dot-product operation has four
phases: reset (0), multiplication (1),
accumulation (2), and conversion (3).
The computation begins at the reset
phase, where the charges stored in C2
are cleared. In phase one, the input
voltage charges the weight capacitor
Cw, which counts as one multiplication
operation. Then, in phase
two, the charges in Cw are redistributed
and most of them accrue in
C2 to complete the accumulation
operation. After n cycles of 1 and
2, the conversion phase is triggered
and the accumulated voltage Vsum is
converted to a digital signal. The first
multiplication phase and the reset
phase of each dot-product operation
can be activated simultaneously because
switch P2 separates them. The
proposed MACUs deals with signed
weights through switches P1 and P1.
While maintaining the differential
inputs within [0,1], the actual input
range is extended to [−1] by the differential
structure.
Three implementation examples
are presented in Figure 19, the first
of which is the Modified National Institute
of Standards and Technology
(MNIST) database image classification
[37]. The five-layer neural network
shown in Figure 19(a) is trained
to classify images in the MNIST data
set. During inference, the first fully
connected layer is operated in the
proposed MACUs. The testing accuracy
is displayed in Figure 19(b).
The standard accuracy refers to the
results acquired from the all-digital
computation. The testing accuracy
increases with the rise of weight resolution.
ADC resolution does not affect
much. When the weight resolution
exceeds 4 b, the accuracy stabilizes at
approximately 95%. In the second application,
a 48-layer convolutional neural
network was trained to denoise speech.
The proposed MACUs were applied to
the 24th convolutional layer. The selected
weight and ADC resolutions are
6 and 8 b, respectively. The simulation
results are shown in Figure 19(c).
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
37
SL CVD MoS2 Growth
100 mm
AFM
1 mm
TEM
1 mm
25
20
15
10
5
E-Mode FET Technology
Gate First
Gate Last
Compact Model Verilog-A Code
15
10
5
-8 -4 04
VT (V)
02 46
VDS (V)
Circuit Design and Simulation
Master
CLK
IN
Slave
CLK
OUT
CLK
CLK
3
Measurement
Simulation
2.5
2
1.5
1
0.5
Measurements
0246 810
ILoad (µA)
Cr/Au/Pd
Al2O3
Ti/Au
FIGURE 14: The design flow for large-scale MoS2 ICs, which includes compact models of MoS2 devices, a schematic design based on simulation results, and a layout with parametrized cells using
industry-standard IC design environment. Then the full chip layout is exported in a graphic database system (GDS) format for mask generation and chip fabrication [32]. CVD: chemical vapor
deposition; TEM: transmission electron microscopy; Au: gold; Pd: palladium; Al2O3: aluminum oxide; Ti: titanium. AFM: atomic force microscopy; SL: single layer.
fsw = 10 kHz
fsw = 50 kHz
fsw = 100 kHz
MoS2 Au
Chip Fabrication
Layout With Parametric Cell
Vout (V)
Count
ID (µA/µm)
IEEE Solid-States Circuits Magazine - Fall 2021

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