40 FALL 2021 IEEE SOLID-STATE CIRCUITS MAGAZINE DCC Reset Cw Vinp P1 P1 P1 P1 Vinn Vsumn Cw DCC (a) φ0 Vin P1 Cw DCC φ2 Vin P1 Cw Reset C2 DCC (c) DCC ADC_EN (d) FIGURE 18: The MACUs overview. (a) An overview of the proposed MACUs, (b) the structure of the digital-to-capacitance converter, (c) operational modes, and (d) the timing diagram [36]. SAR ADC: synthetic aperture radar analog-to-digital converter; DCC: digital-to-capacitance converter; CNTRL: control. C2 Reset Phase Vsum P2 ADC_EN Reset ADC P1 Cw Reset C2 DCC Accumulation Phase Vsum ADC P2 ADC_EN P1 Cw C2 P2 ADC_EN Reset φ3 Vin Conversion Phase Vsum ADC Reset P1 P1 P2 12 P2 φ1 Vin Multiplication Phase Vsum ADC_EN ADC clk (b) MACU Operation ω1 > 0 φ0 φ2 φ1 ω2 > 0 ω3 > 0 φ2 φ1 φ2 φ1 φ3 φ0 Reset P2 P2 C2 Reconfigurable SAR ADC C2 ADC_EN w_sc[2:0] w[5:0] CNTRL S[4:0] P2 C1 2C1 4C1 8C1 16C1 Vsump S0 S1 ADC_EN S2 S3 S4 C2 Vin P1 DCC P2 Vsum Reset 1 2 64 3 3 64 1