52 FALL 2021 IEEE SOLID-STATE CIRCUITS MAGAZINE PFD CP FLL Vctrl_P CKREFX2 X2 CKREF (52 MHz) DTC Gain Calibration α1.Z-1 1-Z-1 KDTC Z-n Φe (n) Offset DTC CKFB RDTC CLSB D1 (b) CKDTC RSlope VSlope CK1 CS1 CK2 VS1 Vsmp CS2 PHE_Sign (n) Freq_Err (n) Even_Cycle (n) +2 +1 -1 (d) FIGURE 9: A DTC-based fractional-N SPLL with a CKREF doubler [26]. (a) PLL system diagram. (b) A schematic of the DTC and SPD. (c) SPD operation. (d) The duty cycle correction DCC principle. NDIV: division ratio. (a) SPD DTC CKFB CKDTC Slope Generator ∆V Vref_adj DAC Σ∆M +1, -1 PHE_Sign NDIV (From DSM) CK2 +1, -1 CLKREF Duty Cycle Calibration Freq_Err 1-Z-1 α2.Z-1 1-Z-1 Even_Cycle +1, -1 NDIV DSM Dcc_Err Pull-in/Push-Back Alternative CLKFB Even_Cycle +1, -1 (c) Dcc_Comp FCW CLKREF CLKREFx2 CLKFB ∆T/2 +1 -1 -2 ∆T/2 +1 +2 +1 -2 -1 -1 Vref Vref V1 V2 GM CKFB (104 MHz) MMD CKVCO CKDTC CK1 Vctrl_I Cl 5-7 GHz VCO PLL Output ∆Φ VSlope VS1 Vsmp Odd Cycle Even Cycle DTC Code