IEEE Solid-States Circuits Magazine - Fall 2021 - 56

transient current at each rising edge
of the CKREF. Consequently, its supply
voltage dips and then recovers during
each cycle. This introduces codedependent
INL and a memory effect,
as the DTC delay for the current code
is also contingent on the previous
cycles' DTC codes, due to the supply
not being fully settled. To speed up
supply settling, a master-slave source
follower regulator [26] can be used
instead of a closed-loop regulation
scheme that has limited bandwidth,
as detailed in Figure 12(a). Moreover,
bleeding current can be added in regulator
to speed up the settling of the
source follower, as the settling time is
defined by transconductance (gm)/C
VDD
0.8 V
+
-
Master
LDO
Vgate
Slave
LDO
R
CKREF
D1
CLSB
DTC Code
CKDTC
Reset
(a)
VDD
CKREF
Vramp
Vprech
IDAC
I-DAC
VDTC
(b)
FIGURE 12: DTC topologies: (a) an RC delay-based DTC and (b) a constant-slope DTC. INL:
integral nonlinearity; LDO: low dropout regulator; I-DAC: current DAC; GND: ground.
56
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
τ
in which fosc is the oscillation frequency,
L is the tank inductance, F is
the noise factor of the circuit, Vosc
is
the oscillation amplitude, and Q is the
tank quality factor.
R
C
Vrst
Vth
Vramp
Vst1
Vst2
Vst3
VDD
GND
Vramp
∆tcmp
n Bit
DTC Core
VDTC
VDTC
Vramp
Vth
∆tcmp
∆tcmp Varies With
Vdly Slope  INL
Slave
LDO
(i.e., the gm of the source follower and
the bypass capacitor, C). The delay
stage, the first inverter buffer, and the
digital control circuit each can have its
own slave branch to reduce the supply-induced
spur.
Alternatively, a dummy path using a
replica DTC controlled by the complementary
delay code was used in [53]
to reduce the code-dependent supply
bounce, at the expense of doubling
the DTC core circuit power consumption
and chip area. Moreover, the DTC
codes can be reset to one during each
cycle to fully discharge the tuning capacitors
before applying the new code.
This helps to further reduce the code
dependency. Employing the preceding
Regulator
design techniques, the RC delay-based
DTC PD has demonstrated low QN,
little thermal noise, and highly linear
performance in state-of-the-art fractional-N
PLLs [25]-[31].
To avoid the aforementioned slopedependent
inverter delay, a constantslope
DTC uses a continuous current
to charge a capacitor (i.e., I/C), as in
Figure 12(b) [54]. The start charging
voltage, Vst, is generated by an n-bit
DAC to obtain the variable delay. This
topology intrinsically provides better
linearity than an RC delay-based one.
However, the current source is not
ideal, and the charging current varies
with the delay code, due to channel
length modulation. The settling error
in Vst also results in nonlinearity.
In addition, the flicker and thermal
noise from the current source make it
difficult for this topology to achieve
very low PN (less than -160 dBc/Hz
at a 100-kHz offset). Recent development
of constant-slope DTCs focuses
on low-power applications [55]-[57].
In [56], a 9-b capacitive bank-based
constant-slope DTC achieved a Tres of
1 ps, INL of 0.8 LSB, and PN of -151 dBc/
Hz at a 100-kHz offset for a CKREF of
50 MHz, while consuming only 36.4 μW.
Low-PN Oscillator Design
There are several oscillators used
Vst
VDTC
for LO generation in a 5G mm-wave
transceiver. A low-PN VCO/DCO is
required in fractional-N PLLs to minimize
the overall integrated jitter. On
the contrary, oscillators in frequency
multipliers operate at a much higher
frequency, with relaxed PN requirements
but a wider tuning range to
support multiple bands. For RF applications,
cross-coupled LC oscillators
are the most common topologies. The
well-known Leeson's PN equation [58]
for cross-coupled LC oscillator can be
rewritten to show that
L ?
VQ
fLF
3
osc
osc
$
2
$
,
(3)
IEEE Solid-States Circuits Magazine - Fall 2021

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