IEEE Solid-States Circuits Magazine - Fall 2021 - 61

without any external loops. However,
the low-jitter performance of ILFMs is
available only when the frequency deviation
of the free-running frequency
of the VCO from the target frequency
(M . fINJ) is sufficiently smaller than the
lock range [68]. Thus, it is typical to
use a background frequency tracking
loop (FTL) to correct the VCO frequency
and continuously minimize the undesired
frequency deviation against
voltage and temperature variations
[39]-[41]. Figure 16 displays a singlePLL-based
LO generator supporting
multiple 5G bands using ILFMs [39].
The 3.7-GHz fractional-N PLL output
is divided by two and then multiplied
by 15 via an ILFM to generate LOs at
28 GHz. Another ILFM is used to obtain
×3 for sub-6-GHz band. The VCOs
inside the ILFMs are quadrature types.
An FTL compares the overlapped area
of INJM_I+ and OUTM_Q+ with that
of INJM_I+ and OUTM_Q- at the moment
of injection of INJM_I+ to tune
the VCO frequency close to M . fINJ.
Overall, the LO generator in Figure 16
achieved 206-fs RMS jitter at 29 GHz.
Note that ILFM reference spurs are
usually higher than those of an integer-N
PLL-based frequency multiplier,
as the CKREF is directly injected into
the VCO, and there is no low-pass filtering
as in a PLL.
Mixer- [28] and harmonic extraction-based
[15], [20], [35] (i.e., relying
on transistor nonlinearity to generate
high-order harmonics) frequency
multipliers are also widely used to
generate a small fixed-multiplication
factor, e.g., M = 1.5, 2, or 3. Since they
are open-loop systems, their circuit
design could be easier compared to
the two preceding topologies. A major
drawback of mixer- and harmonic extraction-based
multipliers is that their
intrinsic nonlinear operation generates
unwanted spurious tones, which
could be quite high (e.g., -20 dBc) and
require one or multiple stages of tuned
LC buffers to suppress them [20], [35].
These LC-buffers increase power consumption
and occupy additional chip
area. Figure 17 presents a 60-GHz
DPLL with implicit frequency tripling
based on harmonic extraction [35].
More engineering efforts are required not
only for frequency synthesis but also low-power,
high-frequency LO signal distribution inside a
wireless transceiver.
A 20-GHz, class F oscillator is used
in the main PLL, and it cogenerates a
strong third harmonic at 60 GHz, due
to class F operation. The main PLL employs
a frequency counter and TDC to
form a first-order DSM. A DTC is used
in the CKREF path to cancel the QE due
to DSM, similar to the PLL topology in
Figure 8(d). To extract the third harmonic,
a tuned 60-GHz LC buffer is
employed, which consumes 10.5 mW.
To suppress the unwanted fundamental
DCO tone, an additional parallel
LC tank resonating at 20 GHz is
placed between the source of M1 and
the ground to degenerate the voltage
gain at 20 GHz (see Figure 17). The
60-GHz LO generation circuit achieved
213-277-fs RMS jitter, with a CKREF of
100 MHz.
Discussion and Outlook
mm-Wave frequency bands (i.e.,
FR2) are starting to gain momentum
through developments that make
mm-wave links viable for the largescale
deployment that will be needed.
The low-jitter fractional-N PLL design
techniques discussed in this article
are applicable to sub-6-GHz and mmwave
bands. Using cascaded PLL and
low-gigahertz fractional-N PLLs followed
by frequency multipliers helps
to achieve the stringent RMS jitter requirement
at FR2 to support 64-QAM
and MIMO operation. The 5G NR standard
is still evolving. Two clear trends
are observed. The first is that the
frequency allocations for 5G NR are
frequently updated as new bands are
made available in different countries,
especially at higher spectrums; e.g.,
the 47-GHz band is under discussion.
The second concerns increased radio
complexity. Similar to sub-6 GHz,
higher-order QAM (e.g., 256 QAM) and
more intra- and interband carrier aggregation
will be needed for mm-wave
frequency bands in the near future.
Both trends demand even lower RMS
jitter, which is ultimately determined
by the CKREF and VCO/DCO after optimizing
the PLL topology and other
circuit blocks.
Although using multicore oscillators
can lower the VCO/DCO PN, the
devices will eventually be limited by
power consumption budgets. Thus,
the CKREF needs to be improved. A
temperature-compensated crystal
oscillator (TCXO) is often used as a
CKREF for mobile phones to meet the
stringent thermal stability requirement
of the global navigation satellite
system (e.g., ±0.5 pulse-position
modulation from -25 to 85 °C). Increasing
the TCXO frequency (e.g.,
from 26 to 76.8 MHz) increases the
system sampling rate and reduces
the noise multiplication factor of the
reference path. However, the higher
the fundamental resonance frequency,
the thinner the crystal is. This
limits the frequency of mainstream
TCXO products to below 100 MHz.
Alternatively, a microelectromechanical
system resonator can operate
at hundreds of megahertz to a few
gigahertz, with a high quality factor,
which is attractive [69], [70].
There are many efforts in industry
to develop high-frequency, low-PN,
and low-power CKREFs with a small
form factor, which becomes more and
more critical for future 5G LO generation.
As to intra- and interband carrier
aggregation, increased number of PLLs
are unavoidable. Thus, the potential
coupling between oscillators needs
to be mitigated via careful frequency
planning, floorplans, and supply regulation
schemes. In addition, the LO distribution
complexity also increases.
More engineering efforts are required
not only for frequency synthesis but
also low-power, high-frequency LO
signal distribution inside a wireless
transceiver.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
61
IEEE Solid-States Circuits Magazine - Fall 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2021
