IEEE Solid-States Circuits Magazine - Fall 2021 - 70

CSC architectures can effectively compress the
traditional FC layers of neural networks on par
with pruning methods.
of the cyclic dilated matrix-vector
multiplication and links the array
of PEs to the array of subbanks in
the IFMAP memory with a high internal
memory bandwidth.
Each PE also incorporates another
static random-access memory that
stores output feature map (OFMAP) Yl
in partitions. The compressed format
Wl
t
given a CSC layer and its IFMAP
X, are partitioned and evenly distributed
between the number of PEs
weight and number of PEs input fmap
memory subbanks, respectively; i.e.,
given a WIRl
t !
of Wl
t
NF the NF parameters
#
and N parameters of the fmap
are equally partitioned and stored in
the number of PEs weight and number
of PEs input fmap subbanks, respectively.
Thus, each of the PEs is designated
to compute 1/(number of PEs)
of the total computation attributed to
the layer and should have direct access
to one and only one partitioned
weight memory at all times as well as
be provided with access to each and
every number of PEs memory subbank
at different computation cycles.
High-Bandwidth Router Adopting
Cyclic Architectures
To effectively tile the computation for
the layer and link the individual input
fmap memory subbanks with the
TABLE 1. COMPRESSING LENET-300-100 BY MEANS OF REPLACING
FC WITH CSCI LAYERS COMPARED TO RELATED PRUNING METHODS.
LAYER
PARAMETERS
(BASELINE)
Index memory required?
FC1
FC2
FC3
Total
Top-1
accuracy
236,000
30,000
1,000
267,000
98.4%
PRUNING
[2]
Yes
8%
9%
26%
8% (12
times)
98.4%
PRUNING
[3]
Yes
1.8%
1.8%
5.5%
1.8% (56
times)
98%
CSCI
(COMPRESSION c)
No
1.5% (84 times)
4.4% (27 times)
100% (one time)
2.2% (46 times)
97.2%
PEs, we design a router that adopts
a cyclic architecture that essentially
implements the modulo operator
existing in (11). The cyclic router is
composed of switches that are controlled
by a state machine driven
with the CSC layer's hyperparameters
to provide a one-to-one cyclic link
between IFMAP subbanks and MAC
units from the PEs.
Figure 4 reflects the idea of tiled
computation by illustrating the operation
between an eight-by-eight
CSC matrix (,N 8=
F ,4=
D )2=
and a vector of size eight, using distributed
IFMAP, OFMAP, and weight
memory units that are interlinked
using a fast router. The hardware is
configured with four two-word input
subbanks, four PEs (with 1 MAC
unit), four eight-word weights, and
four two-word output subbanks. The
total computation for this example is
equal to 32 MAC operations, which is
carried out in eight clock cycles using
a router with switches that takes
advantage of the cyclic structure and
instantly links the computing resources
to the required data. Using a
total of four MAC units to perform 32
MAC operations in eight clock cycles
indicates that the design meets the
maximum achievable performance
with the available resources.
TABLE 2. COMPRESSING ALEXNET BY MEANS OF REPLACING FC
WITH CSCII LAYERS COMPARED TO RELATED PRUNING METHODS.
LAYER
All convolution
layers
FC1
FC2
FC3
Total
Top-5 accuracy
N/A: not applicable.
70
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
PARAMETERS
(BASELINE)
Index memory required?
2.5 million
38 million
17 million
4 million
61 million
79.1%
PRUNING
[2]
Yes
36%
9%
9%
25%
11% (nine
times)
80.2%
PRUNING
[4]
Yes
25%
7%
7%
18%
8% (12
times)
80.4%
CSCII
(COMPRESSION c)
No
100% (N/A)
2% (42 times)
6% (17 times)
33% (three times)
10% (10 times)
77.6%
Configuration and Fabrication
The CSC-AP hardware was configured
to have a data width of 8 b with
16 PEs each incorporating 1 MAC unit,
1 kB of weight memory and 512 B of
Input and 512 B of Output memory, as
illustrated in Figure 3. The configured
hardware was fabricated using Taiwan
Semiconductor Manufacturing Company
CMOS technology in 65 nm on a die
area of 7mm.2
In total, the hardware
has 16 kB of availability for weight
memory, 8 kB for the IFMAP, and 8 kB
for the OFMAP.
For the router, we adopted a CSC
structure with the parameters L 2=
stages, N 16=
switches per stage,
and F 4= degrees of switches,
which provides an internal bandwidth
of 1.6 GB/s at a clock rate of
100 MHz. Figure 5(a) shows the post
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