IEEE Solid-States Circuits Magazine - Fall 2021 - 72
The Performancetrue
indicates the
number of multiplication or addition
operations an accelerator is
able to carry out in a second, and
we measure it in terms of GOPS. The
Efficiencytrue
indicates the number
of multiplication or addition operations
an accelerator is able to perform
per unit of energy, i.e., joules,
and we measure it in terms of giga
operations per joule (GOPJ) or tera
operations per joule (TOPJ). Note
that these metrics are attributed to
an accelerator that performs only
the workload it is given to regardless
of the skipped computation,
hence denoting the metrics with the
subscription true.
On the other hand, for an accelerator
that implements a model whose
computation is reduced by c times
(i.e., ()/,1ccwhich
is reduced using techniques
such as zero-skipping), an equivalent
performance and efficiency can be accounted
for the accelerator that would
take the zero computations into account
using the following relations:
PerformancePerformance
Efficiency
eq
eq
=
=
c
c
#
#
Efficiencytrue
true
.
(13)
For example, the matrix-vector multiplication,
as illustrated in the Figure
4, requires 64 multiplications,
32 of which are zeros that can be
skipped. The matrix can be packed
in a compressed form according to
(10) with two times fewer parameters
that include only nonzero
values, and the matrix-vector multiplication
can be converted to a dilated
matrix-vector multiplication
that includes two times fewer operations.
When a hardware implements
such a matrix-vector multiplication,
it can perform only nonzero multiplications
in eight cycles. Thus, its
true performance can be computed
as 32/8 multiplications per cycle.
However, when the skipped zero
multiplications are also accounted
for, the equivalent performance
is 64/8 multiplications per cycle,
which is two (compression rate)
times the true performance.
72
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
the computation of
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0 15 0 12 0 13 0 14
18 0 19 0 16 0 17 0
0 22 0 23 0 20 0 21
25 0 26 0 27 0 24 0
0 29 0 30 0 31 0 28
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(a)
IFMem: Input Feature Memory
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PE1
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MAC
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High Bandwidth IFMem
Router
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Router
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MAC
PE2
166 247
MAC
PE3
144 225
MAC
PE4
00 0 01 0 02 0 03 0
0 04 0 05 0 06 0 07
11 0 08 0 09 0 10 0
0 15 0 12 0 13 0 14
18 0 19 0 16 0 17 0
0 22 0 23 0 20 0 21
25 0 26 0 27 0 24 0
0 29 0 30 0 31 0 28
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(b)
OFMem: Output Feature Memory
FIGURE 4: The high-bandwidth router that adopts a CSC architecture to implement a CSC DNN layer, illustrated with a simple example: multiplication between a cyclic weight matrix with F = 4, D = 2,
N = 8, and a vector with size eight, using four processing engines and performed in eight cycles. (a) Operate the first diag (cycles 1 and 5). (b) Operate the second diag (cycles 2 and 6). (c) Operate the
third diag (cycles 3 and 7). (d) Operate the fourth diag (cycles 4 and 8). (e) Write back (cycles 9 and 10). Diag: diagonal; WMem: weight memory.
2
15
36
65
102
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29
4
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247
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225
PE1
PE2
PE3
PE4
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7
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5
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3
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R
1
WMem
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196 315
MAC
PE4
00 0 01 0 02 0 03 0
0 04 0 05 0 06 0 07
11 0 08 0 09 0 10 0
0 15 0 12 0 13 0 14
18 0 19 0 16 0 17 0
0 22 0 23 0 20 0 21
25 0 26 0 27 0 24 0
0 29 0 30 0 31 0 28
1
2
3
4
5
6
7
(c)
8
30
60
98
22
52
90
2
19
52
101
166
247
144
225
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49
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199
166
269
196
315
R
R
R
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7
166 269
MAC
PE3
R
R
R
4
5
112 199
MAC
PE2
R
R
R
2
3
OFMem
MAC
10 49
PE1
High Bandwidth IFMem
Router
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R
1
WMem
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PE1
PE2
PE3
PE4
304 470
MAC
PE4
00 0 01 0 02 0 03 0
0 04 0 05 0 06 0 07
11 0 08 0 09 0 10 0
0 15 0 12 0 13 0 14
18 0 19 0 16 0 17 0
0 22 0 23 0 20 0 21
25 0 26 0 27 0 24 0
0 29 0 30 0 31 0 28
1
2
3
4
5
6
7
(d)
18
49
15
38
69
108
155
10
49
112
199
166
269
196
315
28
98
112
214
204
338
304
470
R
R
R
6
7
204 338
MAC
PE3
R
R
R
4
5
112 214
MAC
PE2
R
R
R
2
3
OFMem
High Bandwidth IFMem
Router
MAC
28 98
PE1
R
R
R
1
WMem
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01
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OFMem
28
98
MAC
28/98
PE1
112
214
112/214
MAC
PE2
204
338
204/338
MAC
PE3
304
470
304/470
MAC
PE4
00 0 01 0 02 0 03 0
0 04 0 05 0 06 0 07
11 0 08 0 09 0 10 0
0 15 0 12 0 13 0 14
18 0 19 0 16 0 17 0
0 22 0 23 0 20 0 21
25 0 26 0 27 0 24 0
0 29 0 30 0 31 0 28
(e)
1
2
3
4
5
6
7
28
98
112
214
204
338
304
470
R
R
R
304
470
R
R
R
204
338
R
R
R
112
214
High Bandwidth IFMem
Router
R
R
R
28
98
IEEE Solid-States Circuits Magazine - Fall 2021
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2021
Contents
IEEE Solid-States Circuits Magazine - Fall 2021 - Cover1
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