IEEE Solid-States Circuits Magazine - Fall 2021 - 82

EMIB offers cost, design, and performance
flexibility and has been available in highvolume
production for the past five years.
RC and better thermal conductivity.
Shorter distances and higher density
result in lower power consumption
as well. For example, Intel's hybrid
bonding technology provides
<0.05 pJ/bit energy efficiency with
>10,000 bumps per mm2 [42].
Another important factor in using
technologies for multidie integration
is flexibility and scalability. Co-EMIB
combines Foveros and EMIB to provide
2.5D and 3D connectivity between
dies in a package as shown in
Figure 3, achieving high interconnect
density in both horizontal and vertical
directions. It allows for horizontal
and vertical integration with <50-μm
die-to-die interconnect pitch with either
an active or passive die, enabling
larger than reticle sized base and highdensity
connections to companion die
and stacked die complexes.
Omnidirectional
interconnect
(ODI) can support high-bandwidth
interconnects and direct power delivery
using smaller TSVs and highbandwidth
interconnects [27]. ODI
achieves even greater flexibility by
allowing the mixing of die-to-die microbumps
with copper pillars that
extend to package bumps. Copper
pillars to package bumps are useful
for providing direct connection
to the package for power delivery
and high-speed I/O. Figure 4 shows
the multidie interconnect landscape
from Intel that spans 2.5D and 3D
interconnect technologies and their
combinations to create flexible heterogeneous
integration mechanisms
that can be customized to suit different
applications.
As interconnect pitch scales to below
10-μm, micro-3D heterogeneous
integration is realized via hybrid
bonding, and below 1-μm, nano-3D is
realized using monolithic 3D technologies
where heterogeneity is achieved
at the transistor level. Nano-3D drives
new and exciting possibilities by enEMIB
Die
1
EMIB Bridge Bumps
Die 2
EMIB Bridge Bumps
abling stacking of different transistor
technologies such as combining a gallium
nitride N-type field-effect transistor
with a silicon PMOS transistor to
enable efficient power delivery and
RF solutions, by improving resistance,
inductance, and capacitance (RLC) to
create power, area, and performance
advantages [32]. The various qualitative
tradeoffs of using macro-, micro-,
and nano-3D integration are shown in
Table 1 [33]. The projected 3D landscape
is summarized in Figure 5 [33],
where over time 3D interconnect density
increases and 3D interconnect
pitch decreases. The graph in Figure 5
shows that as pitch reduces, the number
of maximum number of connections
per area increases dramatically.
Micro and macro-3D interconnect
technologies have growing commercial
availability today, while nano-3D
technologies are still very much in the
research phases. These technologies
enable improved performance, power,
and area as they reduce die-to-die RLC.
Recent Examples of
Multidie Integration
There are a wide range of reasons
for employing chiplet based designs.
Foveros
Co-EMIB: Merging EMIB and Foveros Architectures
Stack 1
Stack 2
Bridge
FIGURE 3: Co-EMIB is a combination of EMIB and Foveros.
82
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
IEEE Solid-States Circuits Magazine - Fall 2021

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