IEEE Solid-States Circuits Magazine - Fall 2021 - 84

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Monolithic 3D
Cell
Partitioning
Si Transistor
(Top Device
Layer)
GaN Transistor
(Bottom Device
Layer)
Intel GaN 3DIC
(Then, IEDM 2019)
NAND Array
Hybrid Bond
CMOS
3D NAND
(Hilson, EE Times 23 April 2020)
0.01
Intel Foveros (Ingerly, IEDM 2019)
0.1 110
Pitch (µm)
FIGURE 5: The 3D heterogeneous integration technology landscape. (Source: Paul Fischer, Intel.)
hub of a mix-and-match ecosystem
relies upon widely available industry
standard interconnect, and the
release of AIB into the industry ecosystem
has been foundational to enabling
a universities and startups to
design interoperable chiplets. These
interoperable tiles include highspeed
transceivers, data converters,
silicon photonics, and machine learning
accelerators. FPGAs are a natural
hub for interoperability because they
can be configured to run different
interface protocols, such as PCIe or
HBM, across the physical layer that is
specified in AIB.
Intel's Lakefield was the first
product to utilize Intel's Foveros
3D stacking technology to create a
small x-y footprint and enable innovative
PC form factors (see Figure
6) [36]. It was the first industry
demonstration of logic-on-logic 3D
stacking, which is a major milestone
and paves the way for future
high-volume consumer products.
Intel's Ponte Vecchio uses Co-EMIB,
which is the combination of EMIB
Package on Package Memory
10-nm Compute
22 FFL IO/SoC
2.5D die-to-die interconnect with
Foveros 3D interconnect, to create
a high-performance GPU for super
computers (see Figure 7) [37]. The
product is built out from a total of 47
components, including two base tiles,
16 compute tiles, eight SRAM cache
tiles, two I/O tiles, eight HBM memory
stacks, and 11 EMIB interconnect tiles.
This combination of compute, cache,
memory, and base tiles, in combination
with Co-EMIB, is the foundation
for a high-performance supercomputing
product that would otherwise not
be possible using conventional monolithic
approaches. In this example,
Foveros 3D interconnect is used for
memory stacking, while EMIB is used
to create a compute and I/O complex
that is larger than a reticle.
AMD Zen with V-cache is a recently
Package
FIGURE 6: The Intel's Lakefield processor was the first intercept for Foveros
3D stacking technology.
84
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
announced product that showcases
hybrid bonding 3D stacking technology
[28]. Hybrid bonding enabled 3D
stacking with very high die-to-die
interconnect density, lower RC, and
improved thermal conductivity between
the stacked die. In this example,
3D stacking is being used to increase
the size of the L3 cache and thereby
significantly increasing performance
for gaming applications [28].
100
Functional Unit
Partitioning
3D NAND
[WoW]
System Level
Partitioning
CMOS Image Sensor
[WoW] (Sony)
Broad Commercial Availability
e.g., Intel EMIB, Foveros
Hybrid Bond [WoW]
Hybrid Bond [DoW, DoD]
µBump
Growing Commercial Availability
Prods Announced or HVM
R&D Publications
Max Connections/mm2
IEEE Solid-States Circuits Magazine - Fall 2021

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