IEEE Solid-States Circuits Magazine - Fall 2022 - 12

from a publicity stunt by Bandini Fertilizer
company in anticipation of the
1984 Olympics in Los Angeles. They
created a 100-ft-high pile of manure
and staged mock Olympic events on it
for televised commercials. Thus, the
name Bandini Mountain associates the
dominant PDN impedance peak with
a huge mound of doo-doo, hinting at
the affection that packaging engineers
have for it.
The most remarkable thing about
VDD's Bandini Mountain is its predictability.
While it may show up anywhere
from 10 Mz to 100 MHz, in high
performance packaging it's probably
going to be in the 100-200 MHz range.
Mysteriously, it doesn't seem to evolve
over time with advances in technology
and packaging. It sticks to 100 MHz
like a curse. So, if you're going to have
problems with your power supply, it's
likely to happen around 100 MHz, give
or take a factor of two.
Just to be clear, the Bandini phenomenon
is primarily the work of
two unavoidable IC features: package
inductance and on-chip (meaning
" on-die " ) decoupling capacitance.
(Note that ground will also have inductance.
But it is typically less than
what VDD has and can be included in
the VDD total inductance without a
loss of generality.) There will be several
other minor hills caused by board
inductances and other decoupling
capacitors, but they occur at lower
frequencies and can be engineered to
be less of a nuisance. For the sake of
simplicity, it is usually assumed that
any board, laminate, or intentional
package capacitance is doing its job,
so the package inductance is terminated
in an ac ground off-chip.
Fun fact: What looks like a highimpedance
parallel resonance from
the silicon viewpoint looks like a lowimpedance
series resonance from the
board. Measuring this impedance dip
from outside is the easiest way to
measure the Bandini effect directly.
Indirect methods are provided automatically
by Murphy's Law and include
such wonderful things as a noise
hump in the skirts of your PLL spectrum
at 100 MHz offset.
Threat #2: Loop BADwidth
Having a resonance in your power
supply is bad enough, but having it
occur in the neighborhood of 100 MHz
is awful. Why? Because feedback circuits
don't have the bandwidth to
deal with it.
Most of the analog circuits we care
about use feedback. It's the best way
to make accurate, robust signals,
references, and biases. The self-correcting
nature of feedback is also the
very best defense against power supply
noise or disturbances of any kind
(unless, of course, the disturbance is
coupled to the input). But as frequencies
increase the loop gain begins to
fall, which causes the feedback defenses
to weaken.
You can think of PSRR and crosstalk
in terms of impedance (usually
measured to ground). If the impedance
is low, any small parasitic coupling
capacitors from the node to
VDD or other noisy lines have little
effect. (Imagine it as a voltage divider.)
But if a node or output has high
impedance, it's easy for interference
RESONANCE REFRESHER
Unless you happen to work with switching regulators or RF front ends,
chances are that you have forgotten all about inductors and resonant
circuits. Don't fret: everything you need can be found in Figure S1.
For an inductor and capacitor in parallel, you add the admittance
(1/impedance) of the two elements together to get the admittance
of the combination. But unlike resistors, the impedance and admittances
of these elements are vector quantities, meaning that
they have both magnitude and phase, and the phases of capacitors
and inductors are exactly the opposite, 180° apart. This means
that when added together, there will be some cancellation in the
admittance. At some frequency, the magnitude of the admittance
of the inductor will equal that of the capacitor. In that case, the
cancellation is perfect, and the resulting combination has zero (or
very low) admittance, which is the same as infinite (or very high)
impedance. This is the parallel resonance shown in Figure S1.
Such LC resonators are often referred to as tank circuits by analogy
to some mechanical effect, not because they threaten to " tank "
your project.
If there were no resistance in the circuit, there would be no theoretical
limit on the impedance of a parallel LC combination. But there
is always resistance (unless you are working at a few degrees Kelvin).
The damping effect of the resistance is often expressed as the quality
factor (Q) of the resonance. There must be dozens of different formulas
for Q, but it's easy to think of it as the ratio of peak impedance
12
10
1
C1
L1
1.59 nH
1.59 nF
R1
0.1 Ω
0.1
FIGURE S1: Parallel resonance.
10 MHz
100 MHz
Frequency
1 GHz
to the impedance that the inductor or the capacitor would have on
its own at the resonant frequency. This latter quantity is sometimes
called the characteristic impedance of the tank.
See. That wasn't so hard.
FALL 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
Impedance
" Q "
Capacitor by Itself
Inductor by Itself
IEEE Solid-States Circuits Magazine - Fall 2022

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