IEEE Solid-States Circuits Magazine - Fall 2022 - 25
or operator type with an optimized
core. Examples of this approach are
the combination of NVDLA accelerators
and Tensor cores in GPU systems
[25] or the combination of analog and
digital compute accelerators in our
KU Leuven/imec Diana chip [34] or in
recent work from ETH [6]. The combination
of heterogeneous cores allows
one to make the core sizes larger without
sacrificing too much utilization.
Figure 6(a) represents Diana's hardware
architecture [34], which combines
a low-precision massively parallel analog-in-memory-compute
(AiMC) array
with a digital higher precision smaller
compute array with more flexibility.
This allows one to map the different
layers of an NN on different processor
cores, depending on their layer dimensions
and precision needs. Many classification
networks, like the ResNet
shown in Figure 6(b), operate on larger
feature maps with fewer input/output
512 kB
L2 Memory
256 b
Digital Core
16 OX16 K
AiMC
Core
256 kB
L1 Memory
64 K64 C;
3 Fx; 3 Fy
128 b 512 b 6b ∗ 512
16 OX2 Fx; 2 Fy
Pooling Core
(a)
Digital and
Pooling Core
AiMC
SIMD
Layer 0
100,000
Layer 1
200,000
Layer 2
1e6
1.4
1.2
40% Less
0.8
0.4
Layer
by Layer
(d)
FIGURE 6: An example of a heterogeneous AI processor. Diana [34] combines a digital and an analog-in-memory-compute (AiMC) core.
(a) The hardware architecture diagram. (b) The ResNet workload mapped on the core, color coded to link with (c). (c) The mapping and execution
schedule of the ResNet workload across all cores; interlayer data dependencies are indicated by the lines between the tiles executed on
different cores. (d) The resulting latency and memory footprint benefits stemming from depth-first execution over layer-by-layer execution.
(a) Hardware architecture. (b) Workload. (c) Workload depth-first scheduling on cores. (d) Layer-by-layer versus depth-first scheduling.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2022
25
Depth First
400
200
Layer
by Layer
Depth First
7.1x Less
134 KB
1,000
800
300,000
Layer 3
400,000
500,000
Latency (Clock Cycles)
Layer 4
(c)
Layer 5
600,000
Layer 6
934 KB
700,000
Layer 7
Layer 8
SIMD Core
64 K
224 × 224 × 3 (Height ∗ Width ∗ Channel)
High Precision/Low Parallelism
Digital Core
Pooling Core
L[0]: CONV 112 × 112 × 64
L[1]: MaxPool
L[2]: CONV 56 × 56 × 64
L[4]: CONV 56 × 56 × 64
L[5]: ElemSum
L[6]: CONV 56 × 56 × 64
L[7]: CONV 56 × 56 × 64
L[8]: ElemSum
(b)
L[3]: CONV 56 × 56 × 64
AiMC Core
Low Precision
High Parallelism
SIMD Core
128 b
Latency (Clock Cycles)
512 b
Req. Buffer Size (KB)
IEEE Solid-States Circuits Magazine - Fall 2022
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2022
Contents
IEEE Solid-States Circuits Magazine - Fall 2022 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2022 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2022 - Contents
IEEE Solid-States Circuits Magazine - Fall 2022 - 2
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IEEE Solid-States Circuits Magazine - Fall 2022 - Cover3
IEEE Solid-States Circuits Magazine - Fall 2022 - Cover4
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