IEEE Solid-States Circuits Magazine - Fall 2022 - 7

high at tt ,1= so does
rise causes Q MC3r =
Q ,2
r
and this
to change as
well. Div23 then divides by two, bringing
Q2
back to a high level at tt .2
=
Now, Q3 changes, and Div23 divides
by three until = We observe that
tt .3
the overall circuit acts as a 5' stage.
One can readily show that substituting
the 2' block with a 3' structure
creates a divide ratio of seven. Thus,
the topology illustrated in Figure 2(b)
divides by five if MC 02
seven if MC .12
=
Depicted in Figure 2(c) is a more
general case where the divide
ratio is equal to four if BMC 02
==
(because both stages reduce to 2'
blocks) and equal to six if B = 0 and
MC 12
= (because the second stage
divides by three). In summary, this
arrangement can divide by four,
five, six, or seven according to the
logical levels applied to B and MC2
.
MC
Divider Architecture
To develop a modular chain, we
redraw the
CK
(a)
'23 / circuit of Figure 1(b)
at the latch level in Figure 3(a) but
with one modification. We insert
an AND gate between L1
and L1
l and
control it by an input B. The circuit
divides by three if MC B 1== and by
two if either is low.
In the last step of our development,
we employ two instances of
C2MOSA Divider
VDD
CK
CK
M2
M4
M3
M1
M6
CK
CK
M8 Inv1
M5
M7
W1,5 = 0.5 µm W3,7 = 2 µm
W2,6 = 1 µm W4,8 = 2 µm
(a)
FIGURE 4: The C2
Inv2
P
Inv1,2:
WN,P = 0.5 µm
Q
X
CK
M1
M3
CK
M5
M7
W1,5 = 0.5 µm W3,7 = 2 µm
W2,6 = 1 µm W4,8 = 2 µm
(b)
MOS latches with clocked devices (a) in the signal path and (b) outside the signal path.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2022
7
Inv1,2:
WN,P = 0.5 µm
CK
N
M2
M4
CK
CK
Module 1
L2
Q1
L′1
B1
2/3
Q2
L′2 Q2
L1
MC1
(b)
FIGURE 3: (a) The ÷2/3 circuit at the latch level and (b) two such stages in a loop.
C2MOSB Divider
LREF
VDD
M8
M6
CK1 Q3
L′1
B2
L2
L′2
L1
MC2
Module 2
2/3
Q4
Q4
CK2
B
L1
D Q
L′1
DQ
Q1
L2
L′2
D Q D Q
Q2
Q2
this topology in the form suggested
by Figure 2(c). Illustrated in Figure
3(b), the result receives a " static "
digital input BB
divide ratio. Also, the MC of the first
module is driven by latch L1
in the
following stage [as in Figure 2(b)].
It can be shown that for n such
stages, the divide ratio is equal to
22 BB ,2
nn10 where MCn
++g+
-
n
= and by
1
to 21n 1
+
-
is
assumed to be high [2]. This value
can go from 2n
in steps
of unity. For our target range of 560-
640, we must select n = 9.
Choice of Logic Style
With a maximum input frequency
of 35 GHz, we must implement the
12 that defines its
divider with a logic style that robustly
supports the speed and yet consumes
low power. We prefer to avoid CML
for its static power and surmise that
CMOS (rail-to-rail) logic can deliver
the required performance.
We examine two CMOS logic
styles here, namely, two versions of
the clocked CMOS (C2
MOS) structure
[3]. To quantify their speed limitations,
we use these styles to construct
2' circuits. Figure 4 depicts
the two realizations along with their
transistor dimensions and an output
buffer. Note that the C2
C2MOSB versions simply differ by
how they accommodate the clocked
devices in the stack.
MOSA and
Inv1
Inv2
IEEE Solid-States Circuits Magazine - Fall 2022

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