IEEE Solid-States Circuits Magazine - Fall 2022 - 8

Before evaluating these circuits'
maximum toggle frequencies, we
should make three remarks. First, in
Figure 4(a), the clocked transistors
introduce capacitance directly in the
signal path, whereas in Figure 4(b),
they do not. We then expect C2
MOSB
to achieve a higher speed. Second,
this structure, unfortunately, suffers
from charge sharing. Suppose both
CK and Q are low while P goes low.
Transistor M2
then turns on, allowing
the charge on the capacitance
at node N to be shared with that at
Q. The low level at this node, there0.6
0.8
1
0.4
0.2
0.4
0.45 0.5 0.55 0.6
Time (ns)
VN VQ
FIGURE 5: The divider output showing
kinks in transitions.
100
110
120
50
60
70
80
90
40
0123
WN,P (µm)
FIGURE 6: The maximum divider speed
versus the width of clocked transistors.
C2 MOSA
C2 MOSB
fore, degrades significantly. A similar
effect occurs if Q is high and P rises.
Figure 5 plots the voltage waveforms
at Q and N for an input frequency fin
of 30 GHz, revealing the kinks that
arise from charge sharing. At very
high speeds, nevertheless, the kinks
begin to disappear.
Third, in optimizing frequency
dividers, we typically observe a higher
performance as we increase the
widths of the clocked transistors-because
they present less resistance-
but we must also consider the power
consumption in the clock path. Expressed
as
fC ,VDD
2
in in
this value can,
in fact, exceed that burnt by the data
path. A fair comparison of different
topologies, therefore, requires the
same total Cin
for each. In Figure 4,
the total transistor width in the clock
path is equal to 8 μm.
We examine the maximum speed
of the C2
MOSA and C2
MOSB
' 2 circuits
as the width of the clocked
transistors is varied. Simulations
yield the behavior illustrated in Figure
6. We observe the following:
■ The A style exhibits an optimum;
this is because wider transistors,
in this case, also introduce greater
capacitance in the signal path.
■ For the B style, the speed improves
up to the point where the on-resistance
of the clocked transistors is
several times less than that of the
devices in the data path.
■ Except for the first point on the
left, the B version remains faster
than its A counterpart, confirming
our intuition that placing the
clocked devices directly in the
data path degrades the speed.
■ For a width of 2 µm, the B structure
runs up to an input frequency
of 105 GHz.
0.2
0.4
0.6
0.8
0.4
0.45 0.5 0.55 0.6
Time (ns)
FIGURE 7: The type B divider output with
fin
= 105 GHz.
8
FALL 2022
We then select the B version for the
first stage in Figure 3(b) with a width
of 2 µm while bearing in mind its
charge-sharing issue. Figure 7 depicts
the waveform at node X in Figure 4(b)
with fin
A version appears to lie well above the
range of interest to us, suggesting that
this type should suffice for our purpose.
However, layout parasitics drastically
reduce the speed. Moreover,
' 2 arrangements make optimistic
predictions for circuits having greater
divide ratios. For these reasons, we resort
to the B style for the first module
and design the entire divider for fin
=
60 GHz, expecting that it can operate
at 35 GHz after it is laid out.
Second, in contrast to the conMOS
ceptual
latches in Figure 3(a), C2
topologies do not provide complementary
outputs. As seen in the following
sections, the module design
must be modified accordingly.
Third, given that the second module
in Figure 3(b) presents a large
capacitance to the output of the first
and that it operates at a lower speed,
we wonder whether it can employ
narrower clocked devices. We return
to this point later in the article.
Design of the First Module
The first module in Figure 3(b) poses
the greatest speed challenge. To
accommodate NAND functions, we
modify the topology as illustrated in
Figure 8(a). Inverters Inv1
and Inv2
do
introduce additional delays, but the
alternative would be to employ NOR
gates, which are substantially slower.
Also, these inverters' small transistors
require two-stage buffers Inv ,35
and Inv ,46
for driving the input
capacitance of the next module.
Each NAND/latch combination
is realized as shown in Figure 8(b).
Note that the transistor widths in
the data path are scaled with respect
to those in the reference latch, LREF
in Figure 4(b). The single latch, L2
Figure 8(a), is based on LREF
l in
as well.
We first perform simulations to
= 105 GHz. We shall call LREF
in this figure the " reference " latch, as
it provides the optimal ratios of transistor
widths.
We should raise three other points
here. First, the 61-GHz limit facing the
IEEE SOLID-STATE CIRCUITS MAGAZINE
determine the maximum speed of
this module. We surmise that the
worst case occurs for 3' operation
and examine the waveforms at nodes
E and F in Figure 8(a). Plotted in Figure
9(a) for fin
= 60 GHz, these waveforms
reveal proper operation. The
kinks observed at F are removed by
the following inverters. Figures 9(b) and
(c) show the results in the 2' and 7'
Voltage (V)
Maximum
Input Frequency (GHz)
Voltage (V)
IEEE Solid-States Circuits Magazine - Fall 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2022
