IEEE Solid-States Circuits Magazine - Fall 2022 - 9
Inv3 Inv5
VDD
CK
Inv2
L1
DQ
MC
CK
CK
(a)
FIGURE 8: (a) The latch-level implementation of module 1 and (b) the transistor-level design of the NAND/latch circuit.
0.2
0.4
0.6
0.8
1
0.4 0.45 0.5 0.55 0.6
Time (ns)
(a)
0.2
0.4
0.6
0.8
1
0.4 0.45 0.5 0.55 0.6
Time (ns)
(b)
VE
VF
FIGURE 9: The first module output waveforms in (a) ÷3, (b) ÷2, and (c) ÷7 modes for fin
modes, respectively. Charge-sharing
phenomena are not pronounced at
these frequencies.
We now apply a 30-GHz input and
study the effect of charge sharing.
Depicted in Figure 10(a), the waveforms
at E and F exhibit some kinks.
However, we wonder whether Inv2
and Inv4
in Figure 8(a) incur greater
phase noise (PN) due to the kinks at
their inputs. To answer this question,
we study the PN at the output
of Inv2
in two different cases: (a) the
module operates as a 3' circuit or
(b) the input of this inverter is driven
by an ideal voltage source having
smooth transitions and rise and fall
times equal to 10 ps. As Figure 10(b)
indicates, the PN penalty arising
from the kinks amounts to about
4 dB. Nonetheless, this PN is still far
below that obtained for the millime0.2
0.4
0.6
0.8
1
0.4
0.45 0.5 0.55 0.6
Time (ns)
(a)
VF
VE
-165
-160
-155
-150
-145
-140
-135
-130
-125
104
With Kinks
With Smooth
Transitions
= 60 GHz.
ter-wave VCO designed previously.
For a fair comparison, we raise the
degraded PN profile in Figure 10(b)
by
20 log310dB so as to refer it
=
to the divider input and note that
the result is around -135 dBc/Hz
at 1-MHz offset. The VCO PN, on the
other hand, is approximately equal
to -110 dBc/Hz at this offset.
Having reached a satisfactory
first-stage design, we now compute
its power consumption. According to
simulations, the module of Figure 8(a)
draws 0.4 mW at fin
= 30 GHz in the
0.4 0.45 0.5 0.55 0.6
Time (ns)
(c)
B
Inv1-4:WN,P = 0.5 µm
Inv5,6:
WN = 1µm
WP = 2 µm
Inv1
L′1
L2
CKout
CKout
Inv4 Inv6
L′2
DQ DQ DQ F
E
A
A
B
CK
M2
M4
M5
M3
M1
B
M6
Q
W4,6 = 1 µm
W1,2 = 2 µm W3,5 = 1 µm
(b)
0.2
0.4
0.6
0.8
1
106
108
Offset Frequency (Hz)
(b)
FIGURE 10: (a) The internal waveforms of module 1 for fin
= 30 GHz and (b) the phase noise
profile for the actual circuit and for the case of ideal transitions at node F.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2022
9
Voltage (V)
Voltage (V)
Voltage (V)
Phase Noise (dBc/Hz)
Voltage (V)
IEEE Solid-States Circuits Magazine - Fall 2022
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2022
Contents
IEEE Solid-States Circuits Magazine - Fall 2022 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2022 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2022 - Contents
IEEE Solid-States Circuits Magazine - Fall 2022 - 2
IEEE Solid-States Circuits Magazine - Fall 2022 - 3
IEEE Solid-States Circuits Magazine - Fall 2022 - 4
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IEEE Solid-States Circuits Magazine - Fall 2022 - 9
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IEEE Solid-States Circuits Magazine - Fall 2022 - 84
IEEE Solid-States Circuits Magazine - Fall 2022 - Cover3
IEEE Solid-States Circuits Magazine - Fall 2022 - Cover4
https://www.nxtbook.com/nxtbooks/ieee/mssc_fall2023
https://www.nxtbook.com/nxtbooks/ieee/mssc_summer2023
https://www.nxtbook.com/nxtbooks/ieee/mssc_spring2023
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https://www.nxtbook.com/nxtbooks/ieee/mssc_fall2021
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https://www.nxtbook.com/nxtbooks/ieee/mssc_spring2021
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https://www.nxtbook.com/nxtbooks/ieee/mssc_fall2020
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