IEEE Solid-States Circuits Magazine - Fall 2023 - 23

the 1/f noise. To avoid the large input
range required by closed-loop
neuromodulation artifacts, a highresolution
ADC is required [30], [31].
It makes the IA + ADC framework difficult
to apply to scenarios requiring
more than 100 channels.
On the other hand, the ADC-direct
structure has been used in the literature
to realize the multichannel and
large input range requirements. This
structure is more adaptable to the
CMOS process scaling, showing the
potential for further power and area
reduction. Typical structures include
the open loop VCO-ADC [32] and the
closed-loop ADC based on CT DΣ
modulation [33], [34], [35]. Benefiting
from modern CMOS process scaling,
the VCO-ADC can provide high-voltage
frequency gain, which improves
the input range [32]. In addition, the
dynamic range of the VCO-ADC is
independent of the supply voltage.
Therefore, an open loop VCO-ADC
can realize a low-overhead closed
loop neuromodulation solution with
a 100-mV input range.
CT DΣ modulation-based closed
loop ADC was also used in neural
signal acquisition. The traditional CT
DΣ ADC suffers from the power-area-
performance tradeoff due to its analog
module. Combining noise shaping
and phase/time domain analog processing
techniques, closed loop ADCs
based on CT DΣ modulation have
been proposed [33], [34], [35]. This
offers the possibility of a higher input
range and a lower quantization
noise with low overhead. However,
the noise performance below 1 Hz is
still limited by the flicker noise and
1/f noise of the analog module at the
input end. For signals with a bandwidth
greater than 10 kHz, oversampling
will impose a large overhead on
the DΣ modulator.
On-Chip Neural Signal
Processing Unit
The on-chip neural signal processing
unit (NPU) has been proposed in the
literature to extract
features from
the raw data to reduce the workload
as well as the power consumption of
FIGURE 3: The typical architecture of an on-chip NPU. DT: decision tree; DWT: discrete
wavelet transform; NN: neural network; SVM: support vector machine.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
23
the transmitter. In addition, on-chip
feature extraction is also needed to
close the loop on the chip.
To extract proper features from
the raw data or to generate a decision
based on a segment in a signal stream,
an NPU typically consists of a feature
extractor (FE) and a classifier, as
shown in Figure 3. Machine learning
(ML) and deep learning have grown
by leaps and bounds over the past decade,
which has dramatically shaped
the methods for biomedical signal
processing. According to the different
choices of the FE and classifier, the
NPUs are divided into three types:
1) performs biosignal classification
without a ML classifier, in which a
threshold-based classification is
usually recruited [36], [37], [38], [39]
2) with an ML classifier, such as a
support vector machine (SVM), exploited
[40], [41], [42], [43], [44], [45],
[46], [47], [48], [49], [50]
3) with a neural network (NN) used
as a single classifier or both the
FE and the classifier [51], [52], [53],
[54], [55], [56].
Chn
Ch1
VIP
Biosensor VIN
IA
ADC
DOUT
(a)
Chn
Ch1
VIP
Biosensor VIN
ADC-Direct
DOUT
(b)
FIGURE 2: Block diagrams of (a) traditional IA + ADC structure and (b) ADC-direct
digitizing structure.
NPU
FE
δθ αβ
0 Hz
Median Filter
Classifier
Type 1Type 2Type 3
BPF
30 Hz
FFT
DWT
Threshold SVM
DT
NN
IEEE Solid-States Circuits Magazine - Fall 2023

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