IEEE Solid-States Circuits Magazine - Fall 2023 - 34

followed by an ADC have made significant
advancements in terms of low
power consumption, low noise, and
high ZIN. However, the high gain of
the preamplifier limits the overall DR
of the neural recording AFE, making
it susceptible to stimulation artifacts.
Therefore, researchers have proposed
direct digitization AFEs (DDAFEs),
eliminating the preamplifier and
boosting the DR [23], [46], [47], [48],
[49], [50], [51], [52], [53], [54], [55], [56],
[57]. The DDAFE typically employs
a continuous-time (CT) delta-sigmamodulation
(DSM) ADC structure because
of its ease of driving, inherent
antialiasing property, and high energy
efficiency [49]. An early DDAFE design
uses an open-loop DSM structure [46].
It employs a VCO-based quantizer
to directly convert the neural signal
Neural Signals
(µV-mV)
+
-
LNA
ADC
into the frequency domain and quantize
the signal with first-order noise
shaping [58]. However, the open-loop
nature of this structure limits its DR
to less than 70 dB. Incorporating a
feedback DAC to close the DSM loop
can significantly enhance the DR [58].
(See Figure 4.)
The closed-loop CTDSM typically
comprises an integrator, a quantizer,
and a feedback DAC. The integrator
can be implemented using an active-RC
filter or a Gm-C filter to process the
signal in the voltage domain. Alternatively,
the integrator can process the
signal in the time domain using a VCO.
The active-RC topology offers high linearity
attributed to its closed-loop nature
but has a finite dc ZIN, which is not
ideal for blocking dc offset at the input.
Increasing the ZIN can help address this
Digitized Neural
Recording Data
High Gain (40-60 dB) Moderate Resolution (8-10 bit)
VIN
+
-
VOUT
VCM
VIN
VCM
+
-
VIN
VOUT
DC Coupled
Servo Loop
ZIN
Pseudoresistor
AC Coupled
+
-
#dt
Boost DC Servo Loop
Chopper Stabilized
FIGURE 3: Three types of LNA designs used in the conventional neural recording AFE
structure, which consists of an LNA followed by a moderate-resolution ADC.
Neural Signals (µV-mV)
+
-
ADC
SNDR and DR > 80 dB
VIN
Integrator Quantizer
1
s
Clock
Open-Loop CTDSM
First-Order
Difference
1-z-1
Output
VIN
+
-
DAC
Clock
Closed-Loop CTDSM
FIGURE 4: The basic structure of an open-loop CTDSM and a closed-loop CTDSM in a DDAFE
for neural recording.
34
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
Integrator Quantizer
1
s
Output
Digitized Neural
Recording Data
VOUT
concern, but it may adversely affect
the noise floor of the DSM, potentially
impacting the signal quality. A solution
to this concern involves integrating a
gain stage into the traditional active-RC
CTDSM. This integration converts ZIN
from resistive to capacitive, effectively
creating an infinite dc ZIN [47]. The
Gm-C filter consumes less power than
the active-RC filter but has limited linearity
because of its open-loop structure.
To improve the linearity of the
Gm cell, the work in [48] proposes suppressing
the signal swing at the Gm's
input using a multibit feedback DAC.
Another method suppresses the Gm's
nonlinearity using the gm-boosting
technique [49]. Both methods achieve
an SNDR greater than 80 dB, making
them suitable for neural recording AFE
applications. The VCO-based integrator
is increasingly attractive because of
its robustness against process scaling
and supply voltage reduction. However,
it suffers from poor linearity. One
method for linearizing the VCO-based
integrator is to suppress the signal
swing at the VCO's input. This can be
achieved by implementing a multibit
feedback DAC or applying the differential
pulse code modulation algorithm
[52]. Another approach to linearize
the VCO-based integrator is through
the use of feedforwarding. The study
in [54] proposes implementing a pseudovirtual
ground feedforward technique
in a third-order VCO-based DSM,
achieving a 92.1-dB SNDR with 4.4-μW
power consumption.
In the voltage domain, the closedloop
CTDSM can use a comparator for
1-bit quantization or a SAR-ADC for
multibit quantization. Recently, researchers
have suggested employing
a noise-shaping SAR-ADC as a
quantizer to achieve more aggressive
noise shaping without introducing excessive
loop delay. The work in [23]
presents a quantizer implemented
using a fully passive noise-shaping
SAR-ADC (Figure 5). This design enables
second-order noise shaping
with a single operational transconductance
amplifier, thereby saving area
and improving energy efficiency. In
the time domain, a dedicated counter
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