IEEE Solid-States Circuits Magazine - Fall 2023 - 46

SoC
Dense
DBS Lead Cortical Grid
High-Density
Multisite Sensing
Stimulation/
Disease-Specific
Biomarkers
ML Classifier
Prosthetic Control
Versatile Closed-Loop Neural Interface
(Binary/Multiclass)
TDM FIR
Test Blocks and Flip-Chip Pad Array
4 mm
2.9 mm
TDM
FEE
16-Ch.
Stimulator
(a)
Energy-Aware Regularization
Feature PowerFeature Distribution
CH1
CH2
CH3
16 × 16
Switch Matrix
CH254
CH255
CH256
Column Decoder
Low
64-Ch
TDM AFE
64-Ch
TDM AFE
64-Ch
TDM AFE
64-Ch
TDM AFE
Sigmoid
p = σ(fTw - TH.)
(b)
CH1
CH2
CH3
16 × 16
Switch Matrix
CH254
CH255
CH256
Column Decoder
Channel Index
Memory
(2.93 kB)
Feature Type
Threshold
Weight
Feature Vector
NeuralTree Hardware (≤ 64 MACs/window)
f64
...
f3
w64 w3
f2 f1
Weight Vector
... w2 w1
×
+
Z-1
TH.
(c)
FIGURE 4: NeuralTree: An intelligent, ML-driven closed-loop neural interface [37], [38]. (a) Conceptual system-level diagram, highlighting
high-channel-count cortical arrays and depth leads for high-density sensing and stimulation. (b) NeuralTree's training process involves
256-channel ECoG/LFP sensing, energy-aware regularization, and network pruning. (c) Dynamic inference using an on-chip, versatile,
tree-structured neural network supporting neural signal classification for epilepsy, movement disorders, and BCI. AFE: analog front-end;
FEE: feature extraction engine; HFO: high-frequency oscillation; LL: line length; LMP: local motor potential; LUT: lookup table;
MUX: multiplexer; PAC: phase-amplitude coupling; PLV: phase-locking value; SE: spectral energy; TDM: time-division multiplexing.
46
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
Decision
LUT
Dominant Class
Node Addr
64-Ch
TDM AFE
SE
HFOR
PLV
PAC
MUX
TDM FEE
LL
Hjorth
LMP
Single-Path Inference
f1
fp
w1
Network Pruning
fp
f2
w2
w64
fi
fp
f64
Energy-Aware
Pruning
Features
Extracted
Features
Pruned
High
Temporal
Spectral
Phase
16.6%
81.8%
1.6%
Motion
Control
Dual MUX-CHOP
Dual MUX-CHOP
Class
256-Ch.
Class Labels
CS-TDM AFE
256-Ch. TDM DSL
NeuralTree
3.17 kB
Memory
1.2 mm
2 mm
N
Y
Y
High-Density Neural Activity
for NeuralTree Training

IEEE Solid-States Circuits Magazine - Fall 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2023

Contents
IEEE Solid-States Circuits Magazine - Fall 2023 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2023 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2023 - Contents
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IEEE Solid-States Circuits Magazine - Fall 2023 - Cover3
IEEE Solid-States Circuits Magazine - Fall 2023 - Cover4
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