IEEE Solid-States Circuits Magazine - Fall 2023 - 51

For self-powered IoT applications,
where a VR needs to remain active
while other circuit elements can be in
sleep mode, achieving an extremely
low power consumption (less than
1 nW) [6] and a small area is essential.
Additionally, VRs used in such applications
must exhibit a very low line
regulation (LR) to handle significant
fluctuations in the supply voltage,
which can vary because of environmental
conditions and energy harvester
performance [7], [8]. To address
these requirements, alternative VR
types have gained attention in the IoT
circuit design community. CMOS-only
VRs operating in the picowatt power
range with minimal area requirements
have been developed, utilizing
only a few MOS devices (starting from
only two transistors) [8], [9], [10], [11],
[12], [13], [14], [15], [16], [17], [18], [19],
[20], [21]. However, these circuits suffer
from process-variation sensitivity
and long start-up times. The variability
of the output reference voltage
(Vref) in CMOS-only VRs is fundamentally
high because of the dependence
of MOS transistors on the threshold
voltage (Vth). Moreover, the time required
to charge the large-time-constant
internal nodes to reach proper
operating points is unusually long.
For these reasons, advanced techniques
have been reported recently to
enable CMOS VRs to operate reliably
[8], [12], [19], [20], [21], [22].
To bridge the gap between BGRs
and CMOS VRs, hybrid VR architectures
have been introduced, offering
the advantages of compact size and
picowatt power consumption [23],
[24]. While these hybrids still exhibit
a process sensitivity comparable
to that of CMOS VRs, they have the
potential to compensate for process
variations without significant area or
power penalties [24]. Consequently,
the Vref variability in hybrid VRs approaches
that in traditional BGRs.
The emergence of CMOS and hybrid
VRs has shed light on the unconventional
operating conditions
of analog circuits, involving almostzero-bias
current and operation in
the super cutoff (deep WI) region. This
article aims to provide a comprehensive
overview of the fundamental
operation, design considerations,
and performance limitations of these
types of VRs. By understanding the
unique characteristics and tradeoffs
associated with CMOS and hybrid
VRs, researchers and designers can
make informed decisions when selecting
and implementing VRs for
low-power IoT applications.
CMOS VRs
CMOS VRs can be designed using
a similar approach to that of traditional
BGRs, as illustrated in Figure
1(a). The process involves the
generation of complementary-toabsolute-temperature
(CTAT) and PTAT
voltages, followed by slope adjustment
and combination to obtain a
temperature-independent Vref. The
conceptual temperature behaviors
of PTAT and CTAT voltages, along
with the resulting Vref, are depicted
in Figure 1(b). Note that CMOS VRs
differ from BGRs in that the CTAT
and PTAT voltages are generated
using CMOS transistors instead of
BJTs. As a result, the CMOS Vref is
not associated with VBG but mostly
determined by the discrepancy in
the threshold voltages ()Vth
T
of the
MOSFETs employed in the circuit.
This Vref voltage typically ranges
from approximately 0.15 to 0.3 V,
and the specific value depends on
the process technology utilized.
A MOS VR circuit can also be seen
as a network of a picoampere-current
source connected in series with
a voltage divider circuit formed by
TΩ-MOS pseudoresistors. The constant
current source provides a
channel leakage current that is almost
insensitive to supply voltage
variations. Instead, it is sensitive
to threshold voltage variations [12].
Together with the pseudoresistors,
this current source can generate a
practical value of output voltage.
Notably, this current-to-voltage conversion
incorporates temperature
compensation [10], thereby enabling
the development of an ultra-lowpower
VR design.
V
KPVPTAT
KCVCTAT
T
(b)
FIGURE 1: Temperature compensation in
a VR. CTAT: complementary to absolute
temperature.
Self-Cascode (3T) CMOS VR
The earliest use of CMOS Vref generation
can be traced back to 1979
when the WI self-cascode cell shown
in Figure 2 was introduced [25]. This
circuit consists of two transistors (M1
and M2) with the same bias current
IB. The output voltage is seen as Vref =
VGS2 - VGS1. When IB is able to maintain
WI saturation (VDS > 4VT), the slope
factors of M1 and M2 are assumed to
be identical for simplification (n1 = n2
= n), and the body effect is neglected.
Vref can then be expressed as
VV VnV ln
refth2
, -+ T
^
th1h
J
L
K
K
K
K
c
c
W
W
L
L
m
m
2
1
N
P
O
O
O
O
.
(1)
PTAT
KP
Vref
CTAT
Generation
KC
Slope
Adjustment
(a)
Vref
Combination
IB
W
Vref =~ 9Vth + nVT ln
M1
CTAT
Vref
M2
PTAT
FIGURE 2: Self-cascode circuit.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
51
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IEEE Solid-States Circuits Magazine - Fall 2023

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