IEEE Solid-States Circuits Magazine - Fall 2023 - 52

Here, VT is the thermal voltage,
and the other terms are the respective
transistor parameters. This selfcascode
circuit was used as a PTAT
generator in the BGR reported in [25].
For this reason, M1 and M2 were selected
as similar devices with identical
threshold voltages. By doing so,
only the process-insensitive PTAT
term remains on the right-hand side
of (1), and the PTAT slope can be adjusted
by transistor sizing.
Since the threshold voltage exhibits
CTAT behavior [26], a temperature-compensated
Vref can be
obtained from (1) if the process sensitivity
can be compromised. This
can be achieved by selecting M1 with
Vth_H
V
< -1 mV/K
(Weaker Than VBE)
∆Vth
Vth_L
Weak CTAT
Slope
T
FIGURE 3: Temperature behaviors of
threshold voltages.
a lower threshold voltage than M2
and properly sizing them to align
with the temperature compensation
shown in Figure 1. Please note
that the CTAT slopes derived from
Vth are less pronounced compared
to the slopes exhibited by the baseemitter
junction voltage of a BJT (approximately
-2 mV/K). Therefore, it is
possible to achieve a sufficient PTAT
slope by reasonably sizing M1 and
M2 [15], [16]. Figure 3 shows the conceptual
temperature behaviors of the
threshold voltages Vth_H (associated
with M2) and Vth_L (associated with M1)
and their difference.
The self-cascode VR depicted
IB
M1
Vref
M2
IB
IB
IB
VGS = -Vref
Vref
FIGURE 4: Self-cascode VR and three possible
realizations of IB.
(a)
M1
ID2 = ID1
Vref
M2
W
Vref =~ n
-
2
9Vth + VT ln
FIGURE 5: 2T VR circuit.
52
FALL 2023
L 1
W
L 2
(c)
(d)
FIGURE 6: Possible 2T VR configurations.
IEEE SOLID-STATE CIRCUITS MAGAZINE
Vref
VGS = 0
VGS = 0
Vref
(b)
VGS = 0
Vref
in Figure 2 provides a notable advantage
because of its flexibility in
implementing IB. Figure 4 illustrates
three compact alternatives, where
the precise value of IB is not critical.
By employing these biasing schemes,
the VR can be constructed using just
three transistors, all of which conduct
an extremely low current. In the
options where the gate is connected
to the source, IB is equivalent to the
drain current at zero gate-source voltage
(ID0). Therefore, IB ranges from a
few picoamperes to nanoamperes,
depending on the dimensions of the
bias transistor MB. Alternatively, connecting
the gate of MB to ground is another
option, but it may result in an
impractically low current. To make
this option viable, a native MB with a
zero Vth is typically required. When
considering variations in the supply
voltage, the gate-to-ground option is
preferred as MB also functions as an
additional cascode device, providing
a self-regulated mechanism for the
VR. A detailed discussion on the LR
of a CMOS VR will follow shortly.
2T CMOS VR
A more compact CMOS VR using
only two transistors was invented
in 1986 [9]. The idea of a 2T VR was
then reinvented in [10] and [11] and
later generalized in [12]. The 2T VR
is formed by stacking two types of
NMOS devices, as shown in Figure 5.
The gate terminal of M1 can be connected
to Vref or ground. However, in
line with the self-cascode VR, a gateto-ground
connection is preferred to
achieve a better LR. In this case, M1
will serve as both a cascode transistor
and a current source simultaneously.
To ensure sufficient current
flow while VGS1 is negative, a zeroVth
native transistor is used for M1.
Also, to achieve a sufficiently large
Vref, a thick-oxide or high-Vth device
is preferred for M2 [10], [11]. Again,
neglecting the body effect and gate
leakage current, and setting slope
factors of nn n12
. = for simplification,
the following relationship can
be derived:
V n VV n V ln
refthth h21 T
, -+
22
^
J
L
K
K
K
K
c
c
W
W
L
L
m
m
2
1
N
P
O
O
O
O
.
(2)
By contrast, when M1 is connected
in a gate-to-source configuration,
Vref can be calculated using (1). Both
(1) and (2) offer CTAT and PTAT compensation
via reasonable sizing of
M1 and M2. Figure 6 illustrates all
possible configurations of a 2T VR.
Equation (1) can be applied to derive
Vref in the cases where VGS1 = 0
[Figure 6(b), (c), and (d)]. The circuit
shown in Figure 6(d) is the only one
that does not suffer from the body
effect when implemented in an nwell
CMOS process.
IEEE Solid-States Circuits Magazine - Fall 2023

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