IEEE Solid-States Circuits Magazine - Fall 2023 - 53

When considering the number of
transistors and the expressions for
output voltage, it becomes evident
that the 2T VR is more attractive
compared to the 3T self-cascode VR.
The 2T VR not only offers design
simplicity but also allows for achieving
drain currents as low as a few
tens of picoamperes. By contrast,
the self-cascode VR faces challenges
in maintaining VDS1 (= VGS1) above 4
VT to ensure proper operation in WI
saturation. Consequently, our focus
will be exclusively directed toward
exploring the design considerations
and performance limitations of the
2T VR.
Sensitivity to Power Supply Variation
Figure 7 shows two types of 2T
VRs when subjected to supply voltage
variation. In Figure 7(a), where
VGS1 = 0, the transconductance gm1
is turned off, and only the drainsource
resistance Rds1 forms a Norton
equivalent resistance of IB (RB).
This resistance is then connected
in series with the impedance of the
diode-connected M2 (1/gm2) between
VDD and ground. A supply voltage
variation ()VDD
ation of Vref
T
T
will result in a vari()Vref
solely by voltage
division, as demonstrated here:
1
2
2
V
V
DD
ref
=
gm2
1 + RB
gm2
It should be noted that RB represents
the nonlinear drain-source resistance
of M1, and its value depends
on VDS1. When VDD falls within the
range (),VV V04T
11 +ref
DD
M1 is
biased in the WI triode region, resulting
in a small RB. According to (3),
this small RB will make VV
TT.refDD
(i.e., fully sensitive to supply variation).
When VDD is larger than
VDDmin = Vref + 4VT, M1 will enter the WI
saturation region where /.
Rg1Bm2
&
As a result, this 2T VR becomes less
sensitive to VDD variations.
In the 2T VR configuration where
the gate of M1 is connected to ground
[Figure 7(b)], gm1 is nonzero, thereby
contributing to the isolation between
0.25
0.5
1
VDD, V
FIGURE 8: Large-signal behaviors of 2T
VRs with gate-ground and gate-source
connections in M1.
1.5
(b)
(c)
FIGURE 9: LR enhancement using (a) gate
feedback [23], (b) bulk feedback [28], and
(c) multiloop regulation [27].
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
53
wVref
wVDD
1
~= (gm1 + gm2)RB
Vref
M2
Vref1
M2
0.3
1
=
1 gR+ mB
2
(a)
(b)
FIGURE 7: 2T VRs with (a) gate-source and
(b) gate-ground M1.
wVref
wVDD
1
~= gm2RB
Gate to Source
Gate to Ground
Vref
M2
(a)
Mreg
Mreg1
M1
Vref2
M1
Mreg2
Vref3
VrefN
.
M2
(3)
M2
MregN
Isup
Vref
Vref and VDD. When VDD starts rising
above VDDmin, the supply current (Isup)
increases, causing Vref to rise. As VS1
gets pulled up, VGS1 becomes even
more negative, partially decreasing
Isup. This feedback mechanism results
in
2
2
V
V
DD mm B12
ref
=
1 gg R
1
++
^h
.
(4)
Compared with (3), it is expected
that the LR will improve by approximately
a factor of two for
VV .
DD DDmin
2
In practice, VDDmin can
be as low as 0.5 V [10].
Figure 8 shows the large-signal
behavior of Vref versus VDD for the 2T
VRs in Figure 7(a) and (b). This was
simulated in a 55-nm CMOS technology
using the same type and size of
transistor (thick-oxide NMOS) for M2
and different types of transistors
[low-Vth and native NMOS for Figure
7(a) and (b), respectively] but with
the same channel length for M1 (to
achieve comparable RB). It is clearly
9VDD
M1
RB
Isup
Vref
M1
RB
Mreg
M1
9VDD
seen that connecting the gate of M1 to
ground significantly improves the LR.
LR Enhancement
For some IoT applications that rely
on energy harvesters with highly
fluctuating output voltages, the LR
achieved by the 2T VR in Figure 7(b)
may not be sufficient. An enhancement
technique shown in Figure 9(a)
can be applied without additional
power consumption [23], [24], [27].
It requires an additional regulation
transistor (Mreg) of the same type as
M1 (native NMOS). The gate of Mreg is
connected to Vref instead of ground,
thus forming an additional regulation
loop. This enhances the LR further
by a factor equal to the intrinsic
gain of Mreg.
For some process technologies
that do not offer native NMOS transistors,
a bulk terminal can also be employed
to implement the regulation
loop. For example, in FD-SOI technologies,
it is possible to use the bulk
terminal as a secondary gate with
minimal leakage current. An NMOS
Vref, V
IEEE Solid-States Circuits Magazine - Fall 2023

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