IEEE Solid-States Circuits Magazine - Fall 2023 - 54

VR design utilizing a bulk-feedback
regulation loop in a 22-nm FD-SOI
technology has been recently demonstrated
in [28] and is shown in Figure
9(b). The bulk terminal provides
adequate transconductance to enhance
the LR via the feedback regulation
loop. This VR achieves 0.0004%
LR, showcasing an improvement of
nearly two orders of magnitude when
compared to the LR of 0.03% obtained
from the VR depicted in Figure 7(b)
without Mreg.
When a lower LR is needed, the
regulation technique in Figure 9(a)
can be expanded to include multiple
loops, as shown in Figure 9(c). In contrast
to the VRs in Figure 9(a) and (b),
which can only achieve a low Vref, a
multiloop VR allows precise scaling
of Vref for more general applications
[27]. The VR design reported in [27]
implements two regulation loops
150
200
250
300
350
400
formed by four transistors in a 55-nm
bulk CMOS technology. This VR can
provide output voltages of 0.26 V,
0.52 V, and 0.77 V for Vref1, Vref2, and
Vref3, respectively.
Sensitivity to Process Variation
Since a 2T VR generates a Vref determined
by
TV ,th Vref can be very sensitive
to process variations. Figure 10
illustrates the temperature dependence
of the threshold voltage of an
NMOS transistor for different process
corners. The observed difference
from slow to fast corners can
be as large as 80 mV in sub-100-nm
CMOS technologies [10]. After subtraction,
residual variations of ~30 mV
can still remain, as observed in
the simulation results of Figure 11.
Not only does Vref vary at certain
temperatures, but the temperature
characteristics are also affected,
as evident from the temperature at
which a zero TC is achieved. ComM3
|
80 mV
pared with the result obtained in
the typical corner (blue line), this
zero-TC point shifts toward higher
and lower temperatures for the
slow (red line) and the fast (green
line) corners, respectively. This is
the reason why a large within-wafer
variability (/ )vn of up to 0.8% is
usually obtained, which motivates
the use of additional
trimming
switches to compensate for this
variation [10], [21], [22].
As mentioned before, processvariation
compensation can be
achieved by eliminating Vth from Vref.
Figure 12(a) shows a CMOS VR that
incorporates a compensation mechanism
using bulk biasing [12]. M1 and
M2 in the core 2T VR are now implemented
with the same type of transistor.
Despite the expectation that
they should have the same threshold
voltages and cancel out, M1 now exhibits
a nonzero body bias, resulting
in Vth
T becoming a function of VSB1.
VPTAT
+
-
50
100
Temperature (°C)
TT SS FF
FIGURE 10: Temperature characteristic of
the threshold voltage at different process
corners. T: typical; F: fast; S: slow corners.
For example, TT: typical corner for nMOS,
typical corner for pMOS.
0.26
0.27
0.28
0.29
0.3
0.31
M4
Compensation
(a)
VPTAT
M1
M21
Vref, SS
VrefT, TT
Vref, FF
-20 020 40
Temperature (°C)
60 80
Zero TC
100 120
FIGURE 11: Temperature characteristic of a
2T VR at different process corners.
54
FALL 2023
n-Well to p-Sub
Junction Diode
M22
where c is the body-effect coefficient
and 2 FB
lleak
M2N
(b)
FIGURE 12: Process-compensated CMOS
VR. (a) PTAT bulk-biasing structure and (b)
stacked structure for Vref scaling with its
parasitic diodes.
IEEE SOLID-STATE CIRCUITS MAGAZINE
4 is the surface potential.
Indeed, Vth is eliminated in (5),
and as a result, the VR can provide
a Vref with a within-wafer variability
(/ )vn of 0.26% [12]. If a large Vref is
required, scaling can be achieved
by stacking multiple M2, as shown
in Figure 12(b). This circuit configuration
requires meticulous transistor
sizing to ensure the proper
NVref
M2
2T VR
M1
Vref
As a result, the complete cancellation
of the threshold voltage is no
longer achieved. The compensation
mechanism proposed in [12] consists
of transistors M3 and M4, which are
of the same type as the core devices
and exhibit identical Vth. By conducting
a large-signal analysis, VSG3 can
be determined as Vref in (1), thereby
yielding a PTAT voltage that is almost
process-insensitive [,V 0th
T = with
only the PTAT term of (1) remaining].
In practical terms, assuming that the
bulk current of M1 is negligible compared
to ID3, we obtain the following:
VnVT
24FB m
ref , c
-+
c
24FB
-
nVT
ln
ln
c
c
WL
WL
34
43
WL
WL
21
12
m
m (5)
Vref, V
Vth (mV)
IEEE Solid-States Circuits Magazine - Fall 2023

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