IEEE Solid-States Circuits Magazine - Fall 2023 - 55

cancellation of the PTAT and CTAT
terms in (5).
High Temperature Limit
When considering the CMOS VR depicted
in Figure 12(b) at high temperatures,
the presence of parasitic
diodes formed between the n-wells
and p-type substrate begins to impact
the VR's operating point. This
is due to the increase in reverse bias
leakage current (Ileak) of the diodes
with temperature. The presence of
numerous diodes results in a significant
total leakage current, which
adversely degrades the TC and consequently
imposes limits on the
temperature range of the VR. In [12],
the temperature range is reported to
be restricted to only 0-85 °C.
To address the issue of diode leakage
currents, alternative approaches,
such as the insertion of buffers
[14] or a replica unit [18], have been
proposed. However, these methods
incur notable power and area
penalties. A simple and straightforward
solution involves increasing
the bias current by utilizing a larger
M1 transistor, while preserving the
original size ratio (W/L)1/(W/L)2i. Figure
13 shows the simulation results
of the VR in Figure 12(b) for different
sizes of
M 22 22
/.
88 22 ./ .,
mm
nn corresponding to
supply currents of 15 pA and 60 pA,
respectively) at zero VBS, and three
stacked identical M2 devices. In this
scenario, the temperature range can
be extended by an additional 44 °C
at the expense of additional power
consumption.
Hybrid VRs
A hybrid VR, referred to as the combination
of a single BJT and singlebranch
MOS PTAT generator (shown
in Figure 14), has been recently introduced
[23], [24]. Initially, the idea
of combining the CTAT voltage from
the BJT with the process-insensitive
PTAT voltage seemed promising for
achieving a reliable output reference
voltage. However, this is not
the case as the obtained Vref from
this hybrid VR includes not only the
1.1
1.2
0.8
0.9
1
50
100
150 200
Temperature (°C)
(W/L)1: 8.8 µm/2.2 µm
(W/L)2: 8 µm/10 µm
ID = 60 pA
(W/L)1: 2.2 µm/2.2 µm
(W/L)2: 8 µm/40 µm
ID = 15 pA
FIGURE 13: Simulated temperature characteristics
of VR in Figure 12(b) with different
bias currents.
CTAT, PTAT, and VBG terms but also
the process-sensitive Vth term. When
considering process variations, the
sensitivity of a hybrid VR can be
greater than that of a CMOS 2T VR.
Figure 14(a) illustrates a hybrid
VR configuration that combines a BJT
and an NMOS PTAT generator [23].
In this design, all NMOS devices are
individually placed in deep n-wells,
effectively eliminating the body effect.
The presence of deep n-wells
also mitigates the impact of parasitic
diode leakage currents on the
VR. Consequently, this configuration
achieves a wide operating temperature
range, spanning from 0 to
170 °C. Transistor M1 functions as
a current source, supplying a bias
current ID0 that flows through the
diode-connected core devices M2,
the native regulating transistor Mreg,
and the PNP BJT Qp. The current ID0
is exponentially related to Vth. Although
this VR effectively generates
a process-insensitive VPTAT, Vth becomes
a part of VCTAT and, consequently,
Vref becomes sensitive to
process variations:
VV -- a
n
Vth1
refBG
,
1 mm (. nn and
+ 2 nVTlnc
WL
WL
21
12
T 6 ln^
m
VT2h@
(6)
M2
QP
(a)
where a is a parameter that can
be considered constant in comparison
with the threshold voltage variation
[24], and T is the temperature
in kelvins.
In Figure 14(b), the updated version
of a hybrid VR is presented, featuring
a PMOS PTAT generator. This
configuration eliminates the body effect
without the need for deep n-wells.
This hybrid VR also produces a Vref
defined by (6). However, the standard
n-wells that house the PMOS devices
introduce parasitic diodes similar
to those discussed in Figure 12(b).
Hence, the diode leakage current restricts
the high temperature range to
only 100 °C in the design presented
in [24]. The hybrid VR in Figure 14(b)
has been designed and simulated in a
Mreg
Mreg
M1
Current
Source
Vref
M2
M2
VPTAT
VPTAT
M2
Current
Source
M1
Vref
VCTAT
QP VCTAT
(b)
FIGURE 14: Hybrid VR with (a) NMOS PTAT
[23] and (b) PMOS PTAT [24].
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Vref, FF
Vref, TT
Vref, SS
VCTAT, FF
VCTAT, TT
VCTAT, SS
50
100
Temperature (°C)
FIGURE 15: Temperature characteristic of
the hybrid VR in Figure 14(b) simulated in a
55-nm technology.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
55
Vref, V
44 °C
Voltage (V)
IEEE Solid-States Circuits Magazine - Fall 2023

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