IEEE Solid-States Circuits Magazine - Fall 2023 - 56

CMOS VRs demonstrate their superiority
by achieving the lowest power consumption
and chip area.
55-nm CMOS technology, and its VCTAT
and Vref voltages are plotted in Figure
15 versus temperature for different
process corners. It is evident that VCTAT
is affected by the process corners,
and its variation directly impacts Vref
with an error of ~45 mV from the fast
to the slow corners.
In an effort to reduce the variability
of Vref, it has been demonstrated
in [24] that proper sizing of M1 and M2
in Figure 14(b) can minimize the Vth
variations. Since Vth is not only sensitive
to process but also to the channel
width (refer to Figure 16, where
Vth exhibits high sensitivity to W
for
W 2m1 n introducing the Vth
),
250
300
350
400
T
term into the PTAT component allows
for process compensation.
Figure 17 shows a modified hybrid
VR that offers process compensation.
Initially, M1 and M2 are sized such that
W 1m2
= n and W 20 m
duce a nonzero TV ).th
1 = n (to introSubsequently,
different
multipliers are applied to
M1 and M2 to achieve the total widths
that ensure temperature compensation.
This adjustment allows Vth
T to
TT SS FF
24
Channel Width (µm)
68 10
FIGURE 16: Threshold voltage variations versus
channel width for constant channel length
of 4 μm, simulated using 55-nm model.
be skewed toward process corners,
effectively canceling out the variation
of VCTAT. This results in a process-insensitive
Vref (see the right graph of
Figure 17). The experimental results
presented in [24] demonstrate that the
modified hybrid VR achieves a within-wafer
variability (/ )vn of 0.21%,
slightly surpassing the CMOS VR with
bulk-bias compensation ( /vn = 0.26%)
[12]. This sizing technique can also
be applied to CMOS-only VRs, allowing
for process compensation. Recent
variations of this sizing technique can
be found in [19] and [22].
Figure 18 provides a comprehensive
comparison of power consumption
(at room temperature)
and chip area for the three types of
VRs reviewed in this article. The data
presented in the figure are obtained
from designs that achieve a TC below
100 ppm/°C. It is evident that BGRs are
Mreg
M1
Vref
M2
9Vth+VPTAT
M2
9Vth
Vth1
VCTAT
FT S
FIGURE 17: Hybrid VR with process
compensation.
56
FALL 2023
W1 > W2
L1 = L2
Vref
VCTAT
0.001
0.01
0.1
1
constrained to power levels above
1 nW and chip areas above 0.01 mm2
because of the use of resistors and
BJTs. Hybrid VRs, on the other hand,
can operate below 1 nW but have not
yet reached power levels below 10 pW.
In terms of chip area, hybrid VRs are
still larger than 0.001 mm2 since they
still require a BJT in their construction.
By contrast, CMOS VRs demonstrate
their superiority by achieving
the lowest power consumption and
chip area. While some CMOS VRs are
larger and consume more power compared
to hybrid VRs, this can often be
attributed to the inclusion of additional
circuits aimed at specific purposes,
such as speed enhancement
[19], process-sensitivity cancellation
[12], or compensation of leakage current
in parasitic diodes [14].
Conclusion
In this article we have reviewed the
fundamental operation, design considerations,
and performance limitations
of CMOS and hybrid VRs. The
emergence of these types of VRs has
provided valuable insights into the unconventional
operating conditions of
analog circuits, particularly in terms
of almost-zero-bias current and operation
in the super cutoff (deep WI) region.
CMOS VRs offer picowatt design
solutions providing output voltages
below VBG ()
VV
refth
. T with sensitivity
BGR
CMOS
Hybrid
Power (W)
FIGURE 18: Performance comparison of
state-of-the-art VRs reported in [3], [4], [5],
[10], [12], [16], [17], [18], [19], [20], [21], [22],
[23], and [24].
IEEE SOLID-STATE CIRCUITS MAGAZINE
to process variations. However, compensation
can be achieved through
bulk biasing, making them the most
efficient solutions in terms of area
and power consumption. On the other
hand, hybrid VRs with Vref ≈ VBG - | Vth |
also exhibit process dependence, but
compensation can be accomplished
through transistor sizing. These VRs
consume less than 1 nW and occupy a
comparable area to that of CMOS VRs.
These advancements in VR technology
pave the way for further innovations
and improvements in the development
of efficient biomedical sensing
and sustainable IoT systems.
References
[1] R. J. Widlar, " New developments in IC
voltage regulators, " IEEE J. Solid-State
Vth (mV)
Area (mm2)
1 p
10 p
100 p
1 n
10 n
100 n
1 µ
IEEE Solid-States Circuits Magazine - Fall 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2023
