IEEE Solid-States Circuits Magazine - Fall 2023 - 59

to ESD, using a conservative estimate
of 2% die area, is equivalent to
2 million 300-mm wafers. As technology
and circuits evolve, continuous
innovation is required to meet
on-chip ESD requirements in a costeffective
way.
In addition, over the past 50 years,
a global effort led by the ESDA, has
promoted standardized and effective
ESD control practices. Standardizations
of ESD control programs, such
as ESD S20.20-2021 [2], emphasize
training, protocols, ESD-controlled areas,
ionization, grounding, handling,
auditing, and certification and have
resulted in improved ESD controls
in the IC assembly and test environments.
By following the guidelines
and requirements outlined in these
standards, assembly and test sites
have enhanced their ESD control
programs and reduced the risk of
ESD-related failures. In turn, this has
enabled the industry to lower the ESD
target levels. In 2007, the Industry
Council on ESD target levels, an independent
body of ESD experts with the
mission to review the ESD robustness
requirements of modern IC products,
published a revised HBM componentlevel
qualification target of 1,000 V [3].
In 2008, the council published revi -
sed targets for charged-device model
(CDM) levels, recommending a qualification
target of 250 V, and with
advanced ESD controls in place, the
ESD target levels can be further reduced
[4]. This recommendation was
reached after tracking decades of history
on units shipped across the industry,
highlighting the effectiveness
of the control practices in eliminating
systemic field failures due to ESD
damage. The new recommendations
enable silicon area savings and functional
performance improvements as
the ESD protection on chip is smaller
and has lower parasitic loading on
the pins.
What Is the ESD Design
Specification?
The first challenge for the IC designer
is to confirm the particular
ESD target required for their product.
This will drive decisions on cost
and performance with implications
in circuit architecture, floor planning,
and functional tradeoffs. Component
ESD levels should be defined
with the same scrutiny as other
datasheet parameters and defined
by the ESD controls in the manufacturing
assembly and test facilities.
Table 1 summarizes the changes in
factory controls and minimum targets
over the past two decades.
ESD controls are defined in terms
of the " withstand voltage level, "
which the designer must translate
into a peak current and energy to
use in design. The HBM model can be
translated into a current stress as the
model is defined as a voltage charging
a 100-pF capacitor and discharged
through a fixed 1.5-kΩ resistance.
The CDM represents the discharge
of a charged IC. In CDM, the IC is the
capacitor and the impedance of the
pins/circuit from the discharge network.
Figure 1 is a representation
of the CDM discharge current from
a 500-V CDM stress on different size
packages. The peak current varies
from 1 A to 10 A for the same 500-V
CDM stress, illustrating that the designer
needs to know the die size and
package to get the design targets for
CDM protection [5]. Effective IP reuse
and third-party IP need to be assessed
to a known CDM peak current
level so that this can be feedforward
in IP integration.
Process Technology Advances
The transition from larger feature
sizes to smaller geometries, such as
TABLE 1. A SUMMARY OF THE ESD CONTROL AND TARGET-LEVEL CHANGES
BETWEEN 2000 AND 2025.
ESD FACTORY
CONTROL LEVELS
Before
2000
2023
Company ad hoc
controls
S20.20 standards and
compliance: controls to
100 V in ESD-controlled
area
HUMAN BODY
MODEL TARGET [3]
2-kV HBM
1-kV HBM
CHARGED DEVICE
MODEL TARGET [4]
500-V CDM
250-V CDM
10
12
8
6
4
2
-2
-500
500
1,500
Time (ps)
FIGURE 1: An illustration of the different 500-V CDM current discharge waveforms
for different package and die sizes. TQFP: thin quad flat pack; PLCC: plastic leaded chip
carrier; LLP: lead-less lead-frame package; uSMD: wafer chip scale package,
SC: small outline package. (Source: [5].)
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
59
2,500
3,500
1517BGA
176TQFP
84PLCC
48LLP
5SC70
4µSMD
Current (A)
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