IEEE Solid-States Circuits Magazine - Fall 2023 - 6

THE ANALOG MIND
Behzad Razavi
P
The Design of a Phase Interpolator
Phase interpolators (PIs) find application
in beamforming wireless systems
and in wireline transceivers. The latter
typically employ PIs within their
clock and data recovery (CDR) loops.
In this article, we design a PI for a
56-Gb/s receiver (RX), targeting the
following specifications:
■ operation frequency: 28 GHz
■ phase resolution: 0.4 ps
■ jitter: 1001 fsrms
■ power consumption: 21 mW.
The circuit is realized in a 28-nm
CMOS technology with a supply voltage
of 0.95 V and simulated in the
slow-slow corner at 75 °C. All transistor
drawn lengths are equal to
30 nm. The reader is referred to [1],
[2], [3], [4], and [5] for background
information.
PI Environment
Shown in Figure 1 is a 56-Gb/s RX
example where the in-phase (I) and
quadrature (Q) components of a
28-GHz clock arrive from the transmit
side. The PI generates a clock
phase from the I and Q waveforms
and drives the half-rate CDR loop.
Based on the information provided
by its phase detector, this loop commands
the PI to adjust its output
phase until optimum sampling of
Din
is achieved.
The performance of the PI is characterized
primarily by its phase resolution
and random jitter, both of which
cause the sampling instants to depart
from their ideal points in time. Given
Digital Object Identifier 10.1109/MSSC.2023.3315653
Date of current version: 14 November 2023
6
VDD
2
that Din
b =
in Figure 1 has a bit period
(also called the unit interval) equal to
.
T 17 9ps, we aim for a PI resolution
of 0.4 ps and a root mean-square
(rms) jitter of 1001 fsrms
so that the
overall timing error remains below
1 ps most of the time. Moreover, since
two or four PIs are in practice necessary
for delivering complementary
and/or quadrature clocks to the CDR,
we constrain the power consumption
of a single PI to 2 mW.
General PI Concepts
Figure 2(a) illustrates, as an example,
interpolation by a factor of 2 between
the quadrature inputs, VI
ally, we have () ./VV V 2IQout
andV .Q Ide=+
This
function can be realized by means of
current-mode logic or CMOS (rail-torail)
topologies. For the sake of simplicity,
we pursue the latter. As shown
in Figure 2(b), two identical inverters
can perform interpolation by virtue
of their finite output impedances.
We note that at tt12
= the NMOS transistor
in Inv1 and the PMOS device
in Inv2 are heavily on, fighting each
From Transmitter
IQ
Receiver
28 GHz
Phase
Interpolator
Din
(56 Gb/s)
CDR
Circuit
other. If these two devices have equal
strengths (if the /NP ratio is chosen
properly), then () ./VV V 2IQout
The output is denoted by Vout
. +
to
include the inversion.
Phase interpolation fundamentally
requires that the input transitions
be sufficiently slow. As depicted in
Figure 2(c), if the input edge spacing,
tt ,21
-
times of VI
FIGURE 1: PI environment.
and V ,Q then Vout
is greater than the transition
suffers
from a " kink, " incurring a greater jitter.
The interpolation network of
Figure 2(b) faces two issues. First,
Vout
VI
Inv1
VQ
t1
t12
(a)
t2
t
Inv2
(b)
VI
Vout
VQ
t1
t2
(c)
FIGURE 2: (a) Interpolation by a factor of 2, (b) its simple implementation, and
(c) the kink problem.
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
t
Vout
VI
VDD
2
VQ
https://orcid.org/0000-0003-1168-9205
IEEE Solid-States Circuits Magazine - Fall 2023

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