IEEE Solid-States Circuits Magazine - Fall 2023 - 60

deep submicron and nanometer
technologies, presents new challenges
for ESD protection. The reduced device
dimensions, increased chip
area, and increased integration
require innovative ESD protection
design strategies. In short, the comESD
Window
Normal
Circuit
Operation
Circuit
Damage
Vcrit Voltage (V)
FIGURE 2: The concept of the " ESD window "
represented as the margin between normal
circuit operation and circuit damage.
ponents are intrinsically more difficult
to protect from ESD damage
in 2023 when compared to 2000.
The key failure modes are familiar:
pinholes in the gate oxide; NMOS
parasitic NPN snapback; electrothermal
limits in junctions; and
electromigration limits exceeded
in poly, contact, and metals. The
failure physics is well documented
in literature across multiple generations
of technologies [6]. The
ESD design window, illustrated in
Figure 2, is a simple way of defining
the ideal I-V ESD response of a
plug-in ESD clamp between the operating
window and the region of
permanent damage. This margin
between operation and damage has
shrunk significantly as technology
scales [7]. A few key ESD design parameters
are highlighted in Table 2,
ESD Design Tools
One of the unexpected benefits
of scaling is that the technologies
are better characterized in the
ESD domain. There is much more
awareness of the component I-V
responses to pulsed stress in both
the HBM and CDM time domains,
providing critical information to
designers and the electronic design
automation tool developers. Over
the past few decades, the commercially
available ESD verification
tools have evolved from primitive
TABLE 2. THE COMPONENT SENSITIVITY TO ESD DAMAGE INCREASES AS TECHNOLOGY SCALES, WITH AN EVER SHRINKING
ESD DESIGN WINDOW.
VICTIM
Gate oxide
PHYSICAL DAMAGE
Pinhole in the gate oxide at the source edge
ESD PROTECTION
STRATEGY
Clamp Vgs < Vcrit
Clamp Vgd < Vcrit
Below the critical
level for CDM pulse
Key voltages:
Vdg = drain to the
gate voltage
Vgs = gate to source
voltage
Vds = drain to source
voltage
Parasitic NPN
Junction damage due to NPN snapback
Clamp the Vds <
NPN Vsnap and limit
ESD current
NPN: Vsnap
Vcrit ~ 8 V
NPN: Vsnap
Vcrit ~ 3 V
180-nm CMOS
CDM: Vcrit ~ 18 V
<40-nm CMOS
CDM: Vcrit ~ 3 V
showing a dramatic decrease in the
critical voltages used to define
the ESD window. This defines the
challenge for robust ESD circuit
design and requires innovative solutions
and comprehensive verification
techniques.
Interconnect
Contact via and routing damage due to exceeding
current density limits
Poly resistors,
contacts, metal
routing, and vias
must be sized for the
ESD current
No. of levels of
interconnect
2-5
No. levels of
interconnect
10+
60
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
Current (A)
Primary ESD
Response

IEEE Solid-States Circuits Magazine - Fall 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2023

Contents
IEEE Solid-States Circuits Magazine - Fall 2023 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2023 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2023 - Contents
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IEEE Solid-States Circuits Magazine - Fall 2023 - Cover3
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