IEEE Solid-States Circuits Magazine - Fall 2023 - 61

rule checks to more comprehensive
topology-based checks with
technology information included in
electrical rule checks (ERCs) at the
schematic level. The layout tools
now include parasitic extraction for
metals, which has become critical in
minimizing clamping voltages. The
ERCs and design rule checks highlight
areas of risk, particularly for
HBM analysis, and offer flexibility
to the circuit designer with more
ESD awareness in creating solutions.
While circuit designers are not
expected to be ESD experts, they
must now be competent in running
ESD verification tools and have a solid
understanding of the fundamentals
to disposition tool outputs for
optimum performance.
ESD Integration Opportunity
The ideal ESD protection is effective,
transparent to operation, and
adds zero cost. In principle, this can
be achieved only on some pins when
the circuit can be repurposed to
also " self-protect " under ESD stress.
However, integrating ESD protection
into a circuit while maintaining its
performance and functionality can
be challenging as the circuit simulation
tools include only some of the
physical effects.
Power management ICs with many
low-impedance circuits are good candidates
for ESD self-protection.
The first step is to identify the
existing low-impedance paths in the
design and then assess the maximum
ESD pulse current that can be
supported in these paths. If the level
is sufficient to meet the ESD target,
then the path can be considered
" self-protected. " If it does not meet
the ESD target, then a co-design effort
is required to augment the lowimpedance
path with an explicit ESD
clamp and verify the implementation.
There are some scenarios where
self-protection and co-design are imperative.
For example, RF inputs, now
operating >5 GHz, are particularly
sensitive to parasitic capacitance as
this can degrade the signal and compromise
the functional specifications.
The codevelopment of the RF switch
to maximize the ESD robustness can
result in a more optimum design. Circuit
design techniques to shield the
ESD clamp capacitance from the active
RF path have been demonstrated
using stacked diodes and LC tuning
circuits. Going one step further, the
advantages of SOI have been exploited
to engineer the RF MOS switches
on the antenna pin to always turn
on and fully self-protect under ESD
stress [8]. The low-impedance path is
achieved using a combination of MOS
and parasitic NPN currents.
Power management ICs (PMICs)
with many low-impedance circuits
are good candidates for ESD selfprotection.
In the example shown
in Figure 3(a), the high-side FET and
the low-side FET are large power devices.
Typically, this application has
no explicit ESD on the switch pin
as this could impact efficiency during
switching. The integrated body
diodes of the power FET connected
to the switch pin are typically sufficient
to meet ESD targets. The FETs
are large enough to conduct the ESD
target current if the FETs are on. In
the illustration in Figure 3(b), the
high-side and low-side gate drivers
are modified to turn on during an
ESD event but turn off that feature
when the IC is powered up. This is
ideal to meet component ESD targets
and eliminate the need for the
VIN
High Side Gate
Driver
High Side
FET
HV
ESD
Low Side
FET
GND
Low Side Gate Driver
(a)
(b)
FIGURE 3: A block diagram of a power management IC (PMIC) power output stage including ESD protection. (a) The original power output
stage. (b) The modified ESD self-protecting power output stage. GND: ground; SW: switch; Vin: voltagein.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
61
Low Side
FET
GND
SW
ESD
Detect
Circuit
VIN
High Side
FET
SW

IEEE Solid-States Circuits Magazine - Fall 2023

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