IEEE Solid-States Circuits Magazine - Fall 2023 - 62

36
24
12
8-kv IEC Contact Discharge:
* 30-A First Peak of 1-ns Duration,
* 16-V Second Peak of 50-ns Duration
high-voltage (HV) ESD on chip. This
scheme was demonstrated and different
options for the ESD detect circuit
were described for a large 40-V
open drain LDMOS power switch [9].
In very HV technologies, above
1-kV HBM: 0.8-A Peak of
150-ns Duration
System in the
End-User World
050
Time (ns)
100
Assembly
and Test
IC in an ESD
Controlled Area
FIGURE 4: The differences between the ESD current discharge from the component-level HBM
ESD model [13] and the system-level IEC 6100-4-2 ESD model [11]. (Source: [11], [13].)
System Board
Interface IC
4
5
1
3
2
1
2
3
4
5
Primary TVS
Impedance
Residual Stress
On-Chip ESD Diode
Decoupling Capacitor
200 V, the area associated with an explicit
ESD clamp can be prohibitive.
In very HV environments, an explicit
ESD clamp can also be a reliability
hazard as the noise in the system can
also trigger the low-impedance path
during operation. Device-level solutions
to increase the ESD robustness
have been demonstrated by integrating
parasitic NPNs into guard ring
structures to enhance the current
conduction after the HV circuit has
already started to avalanche. The new
ESD self-protected LDMOS and the HV
junction termination structure in conjunction
with parasitic NPN meet ESD
targets without compromising noise
immunity [10].
FIGURE 5: The concept of primary [transient voltage suppressor (TVS)] and secondary protection
(impedance and on-chip diodes) on an interface IC with pins connected to an external port.
TABLE 3. CONTRASTING CHALLENGES BETWEEN THE COMPONENT LEVEL
AND SYSTEM LEVEL WITH DIFFERENCES IN ESD CONTROL, MODELS, AND
PROTECTION METHODS.
COMPONENT LEVEL
SYSTEM LEVEL
System-Level ESD Design Strategies
The focus on system-level ESD protection
has become more prominent
as the semiconductor content in electronic
systems has increased. vtional
Electrotechnical Commission (IEC)
compliance regulations [11], ISO automotive
standards [12], and a recognition
that explicit protection is needed
to prevent ESD damage that can couple
from the end-user environment to
the IC in the system. IC designers are
now considering the interactions and
vulnerabilities of ICs within the entire
system outside of the " ESD protected
area " and in the end-user environment.
While component ESD models are
ESD control
ESD control programs-wrist
straps, grounding, dissipative
surfaces, ionizers, and safe
handling and storage
ESD models
Human body model (HBM)
and charged device model
(CDM)
ESD protection
62
Integrated on chip
Not possible
IEC61000-4-2 and ISO
10605:
End application-specific
model
In system; board, case, and
critical interfaces
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
sufficient for the controlled ESD environment
of the factory floor, the levels
of ESD strikes from both voltages
and currents can be much greater
in the end-user environment, as illustrated
in Figure 4. The peak current
from the 8-kV IEC 61000-4-2 [11]
discharge that consumer electronics
need to survive is >30× the peak current
of an HBM discharge that a component
is designed to withstand in an
ESD-controlled area.
System-level ESD protection involves
addressing external interfaces,
Current (A)
HBM
IEEE Solid-States Circuits Magazine - Fall 2023

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